JAJSIU8B June 2015 – April 2020 ADS131E08S
Use SCLK as the SPI serial clock to shift in commands and shift out data from the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT pins into and out of the ADS131E08S.
Care must be taken to prevent glitches on SCLK when CS is low. Glitches as small as 1 ns in duration can be interpreted as a valid serial clock. An instruction on DIN is decoded every eight serial clocks. If instructions are suspected of being interrupted erroneously, toggle CS high and back low to reset the SPI interface, placing the device in normal operation.
For a single device, the minimum speed needed for SCLK depends on the number of channels, number of bits of resolution, and output data rate. (For multiple cascaded devices, see the Standard Configuration section.) The SCLK rate limitation, as described by Equation 7, applies to RDATAC mode.
For example, if the ADS131E08S is used with an 8-kSPS mode (24-bit resolution), the minimum SCLK speed is 1.755 MHz to shift out all the data.
Data retrieval can be done either by putting the device in read data continuous mode (RDATAC mode) or reading on demand using the read data command (RDATA). The SCLK rate limitation, as described by Equation 7, applies to RDATAC mode. When using the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. This calculation assumes that there are no other commands issued in between data captures.
There are two methods for transmitting SCLKs to the ADS131E08S to meet the decode timing specification (tSDECODE) illustrated in Figure 1 for multiple byte commands: