JAJSIU8B June 2015 – April 2020 ADS131E08S
DRDY is an output signal that transitions from high to low to indicate that new conversion data are ready. DRDY behavior is determined by whether the device is in RDATAC mode or if the RDATA command is being used to read data on demand. See the RDATAC: Start Read Data Continuous Mode and RDATA: Read Data sections for further details. The CS signal has no effect on the data-ready signal.
When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption.
Figure 37 shows the relationship between DRDY, DOUT, and SCLK during data retrieval. DOUT transitions on the SCLK rising edge. DRDY goes high on the first SCLK falling edge regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. Data starts with the MSB of the status word and then proceeds to the ADC channel data in sequential order (channel 1, channel 2, and so forth). Data for powered down channels appear in the data stream as 0s and are to be ignored.
The DRDY signal is cleared on the first SCLK falling edge regardless of the state of CS. This condition must be taken into consideration if the SPI bus is used to communicate with other devices on the same bus. Figure 38 shows a behavior diagram for DRDY when SCLKs are sent with CS high. Figure 38 shows that no data are clocked out, but the DRDY signal is cleared.