JAJSI11B October   2019  – February 2021 ADS131M08

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Startup Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0110 0110)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Power Metrology Applications
      5. 9.1.5 Multiple Device Configuration
      6. 9.1.6 Code Example
      7. 9.1.7 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement Front-End
        2. 9.2.2.2 Current Measurement Front-End
        3. 9.2.2.3 ADC Setup
        4. 9.2.2.4 Calibration
        5. 9.2.2.5 Formulae
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Behavior
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.5 Formulae

This section describes the formulas used for the power and energy calculations. Voltage and current samples are obtained at a sampling rate of 8000 Hz. All samples that are taken in approximately one-second (1 sec) frames are kept and used to obtain the RMS values for voltage and current for each phase.

Power and energy are calculated for active and reactive energy samples of one frame. These samples are phase-corrected. Then phase active and reactive powers are calculated through the following formulas:

Equation 14. GUID-5042FD17-7191-4590-A1DC-A8BF39CDA0D9-low.gif
Equation 15. GUID-037780CA-89B1-4B01-9011-2791D91C1B23-low.gif
Equation 16. GUID-D4CDE5BC-4909-4899-98B8-48D5EB5314DA-low.gif

where:

  • v[n] = Voltage sample
  • i[n] = Current sample
  • Nsamples = Number of samples in the approximately 1-second frame
  • v[n-n90°] = Voltage sample with a 90° phase shift
  • PACTUAL,ph = Instantaneous actual power for the measured phase
  • PREACTIVE = Instantaneous reactive power for the measured phase
  • PAPPARENT,ph = Instantaneous apparent power for the measured phase

The 90° phase shift approach is used for two reasons:

  1. This approach allows accurate measurement of the reactive power for very small currents
  2. This approach conforms to the measurement method specified by IEC and ANSI standards

The calculated mains frequency is used to calculate the 90° shifted voltage sample. Because the frequency of the mains varies, the mains frequency is first measured accurately to phase shift the voltage samples accordingly.

To get an exact 90° phase shift, interpolation is used between two samples. For these two samples, a voltage sample slightly more than 90 degrees before the current sample and a voltage sample slightly less than 90° before the current sample are used. The phase shift implementation of the application consists of an integer part and a fractional part. The integer part is realized by providing an N samples delay. The fractional part is realized by a one-tap FIR filter.

The cumulative power values can be calculated by summing the per phase power results. The cumulative energy can be calculated by multiplying the cumulative power by the number of samples in the packet.

The host calculates the frequency in terms of samples-per-mains cycle by counting zero crossings of the sine wave. Equation 17 converts this result from a samples-per-mains cycle to Hertz.

Equation 17. Frequency (Hz) = Data rate (samples / second) / Frequency (samples / cycle)

After the active power and apparent power are calculated, the absolute value of the power factor is calculated. In the internal representation of power factor of the system, a positive power factor corresponds to a capacitive load and a negative power factor corresponds to an inductive load. The sign of the internal representation of power factor is determined by whether the current leads or lags voltage, which is determined in the background process. Therefore, Equation 18 and Equation 19 calculate the internal representation of the power factor:

Equation 18. PF = PACTUAL / PAPPARENT, if capacitive load
Equation 19. PF = -PACTUAL / PAPPARENT, if inductive load