SBAS713C May   2015  – January 2017 ADS54J69

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Characteristics
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame Assembly with Decimation
          1. 8.4.2.4.1 JESD Transmitter Interface
          2. 8.4.2.4.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Detailed Register Info
      2. 8.5.2 Example Register Writes
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1 General Registers
          1. 8.5.3.1.1 Register 0h (address = 0h)
          2. 8.5.3.1.2 Register 3h (address = 3h)
          3. 8.5.3.1.3 Register 4h (address = 4h)
          4. 8.5.3.1.4 Register 5h (address = 5h)
          5. 8.5.3.1.5 Register 11h (address = 11h)
        2. 8.5.3.2 Master Page (080h) Registers
          1. 8.5.3.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.3.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.3.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.3.2.6  Register 39h (address = 39h), Master Page (080h)
          7. 8.5.3.2.7  Register 3Ah (address = 3Ah), Master Page (080h)
          8. 8.5.3.2.8  Register 4Fh (address = 4Fh), Master Page (080h)
          9. 8.5.3.2.9  Register 53h (address = 53h), Master Page (080h)
          10. 8.5.3.2.10 Register 54h (address = 54h), Master Page (080h)
          11. 8.5.3.2.11 Register 55h (address = 55h), Master Page (080h)
          12. 8.5.3.2.12 Register 56h (address = 56h), Master Page (080h)
          13. 8.5.3.2.13 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.3.3 ADC Page (0Fh) Registers
          1. 8.5.3.3.1 Registers 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.3.4 Main Digital Page (6800h) Registers
          1. 8.5.3.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.3.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.3.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.3.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.3.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.3.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.3.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.3.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.3.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.3.5 JESD Digital Page (6900h) Registers
          1. 8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.3.5.8 Register 31h (address = 31h), JESD Digital Page (6900h)
          9. 8.5.3.5.9 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.3.6 JESD Analog Page (6A00h) Register
          1. 8.5.3.6.1 Registers 12h-5h (address = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.3.6.3 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          4. 8.5.3.6.4 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Start-Up Sequence

The steps described in Table 60 are the recommended power-up sequence with the ADS54J69 in 20X or 40X mode.

Table 60. Initialization Sequence

STEP SEQUENCE DESCRIPTION PAGE BEING PROGRAMMED COMMENT
1 Power-up the device Bring up IOVDD to 1.15 V before applying power to DVDD. Bring up DVDD to 1.9 V, AVDD to 1.9 V, and AVDD3V to 3.0 V. See the Power Sequencing and Initialization section for power sequence requirements.
2 Reset the device Hardware reset
Apply a hardware reset by pulsing pin 48 (low->high->low). A hardware reset clears all registers to their default values.
Software reset: Register writes equivalent to a hardware reset are:
Write address 0-000h with 81h. General register Reset registers in the ADC page and master page of the analog bank This bit is a self-clearing bit.
This bit is a self-clearing bit.
Write address 4-001h with 00h and address 4-002h with 00h. Unused page Clear any unwanted content from the unused pages of the JESD bank.
Write address 4-003h with 00h and address 4-004h with 68h. Select the main digital page of the JESD bank.
Write address 6-0F7h with 01h for channel A. Main digital page
(JESD bank)
Use the DIG RESET register bit to reset all pages in the JESD bank.
This bit is a self-clearing bit.
Write address 6-000h with 01h, then address 6-000h with 00h. Pulse the PULSE RESET register bit for both channels.
3 Performance modes Write address 0-011h with 80h. Select the master page of the analog bank.
Write address 0-059h with 20h. Master page
(analog bank)
Set the ALWAYS WRITE 1 bit.
4 Program registers for
20X or 40X serialization
and program the HPF or LPF filter
The JESD mode (in the JESD digital page) and JESD PLL mode (in the JESD analog page) register bits control 20X or 40X serialization. By default after reset, the device is in 20X serialization mode (4-lanes output).
Write address 4-003h with 00h and address 4-004h with 69h. Select the JESD digital page.
Write address 6-000h with 80h. JESD
digital page
(JESD bank)
Set the CTRL K bit for both channels to program K for the SYSREF signal frequency in step 5.
Write address 6-001h with 01h. Enable 20X serialization (4-lane output, default setting after reset).
Write address 6-001h with 02h. Enable 40X serialization (2-lane output).
Write address 4-003h with 00h and address 4-004h with 6Ah. JESD
analog page
(JESD bank)
Select the JESD analog page.
Write address 6-016h with 00h Enable 20X serialization (4-lane output, default setting after reset).
Write address 6-016h with 02h To enable 40X serialization (2-lane output).
Write address 4-003h with 00h and address 4-004h with 68h. Main digital page
(JESD bank)
Select the main digital page.
Write address 6-052h with 80h and address 6-072h with 08h. Set the ALWAYS WRITE 1 bit (enables correct order of the JESD output lanes).
Write address 6-04Dh with 08h Enable the decimation filter programming.
Write address 6-041h with 12h Enable the low-pass filter (default setting after reset).
Write address 6-041h with 16h Enable the high-pass filter.
Write address 6-000h with 01h and address 6-000h with 00h. Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed.
5 Set the value of K and the SYSREF signal frequency accordingly Write address 4-003h with 00h and address 4-004h with 69h. Select the JESD digital page.
Write address 6-006h with XXh (choose the value of K). JESD
digital page
(JESD bank)
Default value of K is 8 for 20X (4-lane) mode and 4 for 40X (2-lane) mode. However, K can be programmed for higher values than the default by using bits 4-0 of address 6-006 in the JESD digital page. For example, if K = 31 by writing address 6-006h with 1Fh in the JESD digital page, then the SYSREF signal frequency must be kept less than or equal to 250 MHz / 32 = 7.8125 MHz.
6 JESD lane alignment Pull the SYNC pin (pin 63) low. Transmit K28.5 characters.
Pull the SYNC pin high. After the receiver is synchronized, initiate an ILA phase and subsequent transmissions of ADC data.

Hardware Reset

Figure 129 and Table 61 show the timing for a hardware reset.

ADS54J69 hardware_reset_tmng_dgm_sbas706.gif Figure 129. Hardware Reset Timing Diagram

Table 61. Timing Requirements for Figure 129

MIN TYP MAX UNIT
t1 Power-on delay from power-up to active high RESET pulse 1 ms
t2 Reset pulse duration: active high RESET pulse duration 10 ns
t3 Register write delay: delay from RESET disable to SEN active 100 ns

SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 98 dB for a 16-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies. The decimation-by-2 process gives approximately an additional 3-dB improvement in SNR.

Equation 4. ADS54J69 sgnl_to_noise_ratio_eq_sbas713.gif

The SNR limitation resulting from the sample clock jitter can be calculated by Equation 5:

Equation 5. ADS54J69 snr_limitation_eq_sbas706.png

The total clock jitter (TJitter) has two components: the internal aperture jitter (145 fS) is set by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6:

Equation 6. ADS54J69 total_jitter_eq_sbas706.png

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADS54J69 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 130.

ADS54J69 D052_SBAS756.gif Figure 130. SNR versus Input Frequency and External Clock Jitter

Half-band decimation filtering employed by the ADS54J69 reduces the affect of all contributors to SNR by 3 dB. Filtering makes the SNR curve in Figure 130 start at 74 dBFS despite a thermal noise of 71.1 dBFS.

Decimation filtering also improves the affect of jitter noise by 3 dB, and is equivalent to having 102 fS as the effective aperture jitter instead of 120 fS.

Typical Application

The ADS54J69 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 131.

ADS54J69 ac_cpld_rcvr_sbas706.gif

NOTE:

GND = AGND and DGND connected in the PCB layout.
Figure 131. AC-Coupled Receiver

Design Requirements

Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC inputs. When designing dc driving circuits, the ADC input impedance must be considered. Figure 132 and Figure 133 show the impedance (ZIN = RIN || CIN) across the ADC input pins.

ADS54J69 D103_SBAS685.gif
Figure 132. RIN vs Input Frequency
ADS54J69 D102_SBAS685.gif
Figure 133. CIN vs Input Frequency

By using the simple drive circuit of Figure 134, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

ADS54J69 ai_input_drive_cir_bas591.gif Figure 134. Input Drive Circuit

Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 134.

Application Curves

Figure 135 and Figure 136 show the typical performance at 170 MHz and 230 MHz, respectively.

ADS54J69 D003_SBAS713.gif
SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS;
THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc;
IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc
Figure 135. FFT for 170-MHz Input Signal
ADS54J69 D005_SBAS713.gif
SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS;
THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc;
IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc
Figure 136. FFT for 310-MHz Input Signal