SBAS601H December   2012  – July 2014 AFE4400

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Transmitter Power Path
        2. 8.3.5.2 LED Power Reduction During Periods of Inactivity
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The AFE4400 is a complete analog front-end (AFE) solution targeted for pulse oximeter applications. The device consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI interface. The Functional Block Diagram section provides a detailed block diagram for the AFE4400. The blocks are described in more detail in the following sections.

8.2 Functional Block Diagram

ai_fbd_bas602.gif

8.3 Feature Description

8.3.1 Receiver Channel

This section describes the functionality of the receiver channel.

8.3.1.1 Receiver Front-End

The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier (TIA) that converts the input photodiode current into an appropriate voltage, as shown in Figure 34. The feedback resistor of the amplifier (RF) is programmable to support a wide range of photodiode currents. Available RF values include:
1 MΩ, 500 kΩ, 250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ.

The device is ideally suited as a front-end for a PPG (photoplethysmography) application. In such an application, the light from the LED is reflected (or transmitted) from (or through) the various components inside the body (such as blood, tissue, and so forth) and are received by the photodiode. The signal received by the photodiode has three distinct components:

  1. A pulsatile or ac component that arises as a result of the changes in blood volume through the arteries.
  2. A constant dc signal that is reflected or transmitted from the time invariant components in the path of light. This constant dc component is referred to as the pleth signal.
  3. Ambient light entering the photodiode.
The ac component is usually a small fraction of the pleth component, with the ratio referred to as the perfusion index (PI). Thus, the allowed signal chain gain is usually determined by the amplitude of the dc component.

ai_rx_frontend_bas602.gifFigure 34. Receiver Front-End

The RF amplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensure that the low-pass filter RC time constant has sufficiently high bandwidth (as shown by Equation 1) because the input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available CF values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used.

Equation 1. q_rfcf_bas602.gif

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and 12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage allows for more of the available ADC dynamic range to be used.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on, the amplifier output is filtered and sampled on capacitor CLED2. Similarly, the LED1 signal is sampled on the CLED1 capacitor when LED1 is on. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to estimate the ambient signal on capacitors CLED2_amb and CLED1_amb.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx sample time is used for all dynamic range calculations; the minimum time recommended is 50 µs. While the AFE4400 can support pulse widths lower than 50 us, having too low a pulse width could result in a degraded signal and noise from the photodiode.

A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions are meant to be staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so on.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.

8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block

The receiver provides digital samples corresponding to ambient duration. The host processor (external to the AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then set the value of the ambient cancellation DAC using the SPI, as shown in Figure 35.

ai_ambient_cancel_loop_closed_bas602.gifFigure 35. Ambient Cancellation Loop (Closed by the Host Processor)

Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth component of the received signal; see Figure 36. The amplifier gain is programmable to 0 dB, 3.5 dB, 6 dB,
9.5 dB, and 12 dB.

ai_frontend_iv_amp_bas602.gifFigure 36. Front-End (I-V Amplifier and Cancellation Stage)

The differential output of the second stage is VDIFF, as given by Equation 2:

Equation 2. q_vdiff_bas602.gif

where

  • RI = 100 kΩ,
  • IPLETH = photodiode current pleth component,
  • IAMB = photodiode current ambient component, and
  • ICANCEL = the cancellation current DAC value (as estimated by the host processor).

RG values with various gain settings are listed in Table 1.

Table 1. RG Values

GAIN RG(kΩ)
0 (x1) 100
3.5 (x1.5) 150
6 (x2) 200
9.5 (x3) 300
12 (x4) 400

8.3.1.3 Receiver Control Signals

LED2 sample phase (SLED2 or SR): When this signal is high, the amplifier output corresponds to the LED2 on-time. The amplifier output is filtered and sampled into capacitor CLED2. To avoid settling effects resulting from the LED or cable, program SLED2 to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (SLED2_amb or SR_amb): When this signal is high, the amplifier output corresponds to the LED2 off-time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and sampled into capacitor CLED2_amb.

LED1 sample phase (SLED1 or SIR): When this signal is high, the amplifier output corresponds to the LED1 on-time. The amplifier output is filtered and sampled into capacitor CLED1. To avoid settling effects resulting from the LED or cable, program SLED1 to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (SLED1_amb or SIR_amb): When this signal is high, the amplifier output corresponds to the LED1 off-time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and sampled into capacitor CLED1_amb.

LED2 convert phase (CONVLED2 or CONVR): When this signal is high, the voltage sampled on CLED2 is buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample.

Ambient convert phases (CONVLED2_amb or CONVR_amb, CONVLED1_ambor CONVIR_amb): When this signal is high, the voltage sampled on CLED2_amb (or CLED1_amb) is buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code corresponding to the ambient sample.

LED1 convert phase (CONVLED1 or CONVIR): When this signal is high, the voltage sampled on CLED1 is buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample.

8.3.1.4 Receiver Timing

See Figure 37 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and the ADC conversion times for each channel. Figure 37 shows the timing for a case where each phase occupies 25% of the pulse repetition period. However, this percentage is not a requirement. In cases where the device is operated with low pulse repetition frequency (PRF) or low LED pulse durations, the active portion of the pulse repetition period can be reduced. Using the dynamic power-down feature, the overall power consumption can be significantly reduced.

ai_rx_timing_bas602.gif
NOTE: Relationship to the AFE4400 EVM is: LED1 = IR and LED2 = RED.
Figure 37. Rx Timing Diagram

8.3.2 Clocking and Timing Signal Generation

The crystal oscillator generates a master clock signal using an external crystal. In the default mode, a divide-by-2 block converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller. The clocking functionality is shown in Figure 38.

ai_afe_clocking_bas602.gifFigure 38. AFE Clocking

8.3.3 Timer Module

See Figure 39 for a timing diagram detailing the various timing edges that are programmable using the timer module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit counter (running off of the 4-MHz clock) to set the time-base.

All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to 0.

ai_afe_ctrl_signals_bas602.gif
NOTE: Programmable edges are shown in blue and red.
Figure 39. AFE Control Signals

For the timing signals in Figure 37, the start and stop edge positions are programmable with respect to the PRF period. Each signal uses a separate timer compare module that compares the counter value with preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI interface.

After the counter value has exceeded the stop reference value, the output signal is set. When the counter value equals the stop reference value, the output signal is reset. Figure 40 shows a diagram of the timer compare register. With a 4-MHz clock, the edge placement resolution is 0.25 µs.

ai_compare_reg_bas602.gifFigure 40. Compare Register

The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four sets of start and stop registers to control the ADC conversion signal, as shown in Figure 41.

ai_timer_module_bas602.gifFigure 41. Timer Module

8.3.3.1 Using the Timer Module

The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles. These timing instants and the corresponding registers are listed in Table 2.

Note that the device does not restrict the values in these registers; thus, the start and end edges can be positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration of one clock cycle. The following steps describe the timer sequencing configuration:

  1. With respect to the start of the PRP period (indicated by timing instant t0 in Figure 42), the following sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1 ambient.
  2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respective conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2.
  3. Finally, align the edges for the two LED pulses with the respective sampling instants.

Table 2. Clock Edge Mapping to SPI Registers

TIME INSTANT (See Figure 42 and Figure 43) DESCRIPTION CORRESPONDING REGISTER ADDRESS AND REGISTER BITS EXAMPLE(1) (Decimal)
t0 Start of pulse repetition period No register control
t1 Start of sample LED2 pulse LED2STC[15:0], register 01h 6050
t2 End of sample LED2 pulse LED2ENDC[15:0], register 02h 7998
t3 Start of LED2 pulse LED2LEDSTC[15:0], register 03h 6000
t4 End of LED2 pulse LED2LEDENDC[15:0], register 04h 7999
t5 Start of sample LED2 ambient pulse ALED2STC[15:0], register 05h 50
t6 End of sample LED2 ambient pulse ALED2ENDC[15:0], register 06h 1998
t7 Start of sample LED1 pulse LED1STC[15:0], register 07h 2050
t8 End of sample LED1 pulse LED1ENDC[15:0], register 08h 3998
t9 Start of LED1 pulse LED1LEDSTC[15:0], register 09h 2000
t10 End of LED1 pulse LED1LEDENDC[15:0], register 0Ah 3999
t11 Start of sample LED1 ambient pulse ALED1STC[15:0], register 0Bh 4050
t12 End of sample LED1 ambient pulse ALED1ENDC[15:0], register 0Ch 5998
t13 Start of convert LED2 pulse LED2CONVST[15:0], register 0Dh
Must start one AFE clock cycle after the ADC reset pulse ends.
4
t14 End of convert LED2 pulse LED2CONVEND[15:0], register 0Eh 1999
t15 Start of convert LED2 ambient pulse ALED2CONVST[15:0], register 0Fh
Must start one AFE clock cycle after the ADC reset pulse ends.
2004
t16 End of convert LED2 ambient pulse ALED2CONVEND[15:0], register 10h 3999
t17 Start of convert LED1 pulse LED1CONVST[15:0], register 11h
Must start one AFE clock cycle after the ADC reset pulse ends.
4004
t18 End of convert LED1 pulse LED1CONVEND[15:0], register 12h 5999
t19 Start of convert LED1 ambient pulse ALED1CONVST[15:0], register 13h
Must start one AFE clock cycle after the ADC reset pulse ends.
6004
t20 End of convert LED1 ambient pulse ALED1CONVEND[15:0], register 14h 7999
t21 Start of first ADC conversion reset pulse ADCRSTSTCT0[15:0], register 15h 0
t22 End of first ADC conversion reset pulse(2) ADCRSTENDCT0[15:0], register 16h 3
t23 Start of second ADC conversion reset pulse ADCRSTSTCT1[15:0], register 17h 2000
t24 End of second ADC conversion reset pulse(2) ADCRSTENDCT1[15:0], register 18h 2003
t25 Start of third ADC conversion reset pulse ADCRSTSTCT2[15:0], register 19h 4000
t26 End of third ADC conversion reset pulse(2) ADCRSTENDCT2[15:0], register 1Ah 4003
t27 Start of fourth ADC conversion reset pulse ADCRSTSTCT3[15:0], register 1Bh 6000
t28 End of fourth ADC conversion reset pulse(2) ADCRSTENDCT3[15:0], register 1Ch 6003
t29 End of pulse repetition period PRPCOUNT[15:0], register 1Dh 7999
(1) Values are based off of a pulse repetition frequency (PRF) = 500 Hz and duty cycle = 25%.
(2) See Figure 43, note 2 for the effect of the ADC reset time crosstalk.
ai_prog_clk_edges_bas602.gif
1. RED = LED2, IR = LED1.
2. A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28.
Figure 42. Programmable Clock Edges(1)(2)
ai_relationship_adc_reset-conv_bas602.gif
1. RED = LED2, IR = LED1.
2. A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28.
Figure 43. Relationship Between the ADC Reset and ADC Conversion Signals(1)(2)

8.3.4 Receiver Subsystem Power Path

The block diagram in Figure 44 shows the AFE4400 Rx subsystem power routing. Internal LDOs running off RX_ANA_SUP and RX_DIG_SUP generate the 1.8-V supplies required to drive the internal blocks. The two receive supplies could be shorted to a single supply on the board.

ai_rx_subsys_pwr_routing_bas602.gifFigure 44. Receive Subsystem Power Routing

8.3.5 Transmit Section

The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. This integration is designed to meet a dynamic range of better than 105 dB (based on a 1-sigma LED current noise).

The RED and IR LED reference currents can be independently set. The current source (ILED) locally regulates and ensures that the actual LED current tracks the specified reference. The transmitter section uses an internal 0.5-V reference voltage for operation. This reference voltage is available on the REF_TX pin and must be decoupled to ground with a 2.2-μF capacitor. The TX_REF voltage is derived from the TX_CTRL_SUP. The maximum LED current setting supports up to 50-mA LED current.

Note that reducing the value of the band-gap reference capacitor on pin 7 reduces the time required for the device to wake-up and settle. However, this reduction in time is a trade-off between wake-up time and noise performance.

The minimum LED_DRV_SUP voltage required for operation depends on:

  • Voltage drop across the LED (VLED),
  • Voltage drop across the external cable, connector, and any other component in series with the LED (VCABLE), and
  • Transmitter reference voltage.

Using the internal 0.5-V reference voltage, the minimum LED_DRV_SUP voltage can be as low as 3.0 V, provided that [3.0 V – (VLED + VCABLE) > 1.4 V] is met.

See the Recommended Operating Conditions table for further details.

Two LED driver schemes are supported:

  • An H-bridge drive for a two-terminal back-to-back LED package; see Figure 45.
  • A push-pull drive for a three-terminal LED package; see Figure 46.

ai_transmit_hbridge_bas601.gifFigure 45. Transmit: H-Bridge Drive
ai_transmit_push-pull_bas601.gifFigure 46. Transmit: Push-Pull LED Drive for Common Anode LED Configuration

8.3.5.1 Transmitter Power Path

The block diagram in Figure 47 shows the AFE4400 Tx subsystem power routing.

ai_tx_subsys_pwr_route_bas601.gifFigure 47. Transmit Subsystem Power Routing

8.3.5.2 LED Power Reduction During Periods of Inactivity

The diagram in Figure 48 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore, the TIMEREN bit in the CONTROL1 register should be disabled by setting the value to 0.

Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 48) inherent to the timer function. The dimmed appearance does not effect the ambient light level measurement because during the ambient cycle, LED_ON is turned off for the duration of the ambient measurement.

ai_led_bias_bas601.gifFigure 48. LED Bias Current

8.4 Device Functional Modes

8.4.1 ADC Operation and Averaging Module

After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 43). Each ADC conversion takes 50 µs.

The ADC operates with averaging. The averaging module averages multiple ADC samples and reduces noise to improve dynamic range. Figure 49 shows a diagram of the averaging module. The ADC output format is in 22-bit twos complement, as shown in Figure 50. The two MSB bits of the 24-bit data can be ignored.

ai_averaging_module_bas602.gifFigure 49. Averaging Module
Figure 50. 22-Bit Word
23 22 21 20 19 18 17 16 15 14 13 12
Ignore 22-Bit ADC Code, MSB to LSB
11 10 9 8 7 6 5 4 3 2 1 0
22-Bit ADC Code, MSB to LSB

Table 3 shows the mapping of the input voltage to the ADC to its output code.

Table 3. ADC Input Voltage Mapping

DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT 22-BIT ADC OUTPUT CODE
–1.2 V 1000000000000000000000
(–1.2 / 221) V 1111111111111111111111
0 0000000000000000000000
(1.2 / 221) V 0000000000000000000001
1.2 V 0111111111111111111111

The data format is binary twos complement format, MSB-first. Because the TIA has a full-scale range of ±1 V, TI recommends that the input to the ADC does not exceed ±1 V, which is approximately 80% of its full-scale.

In cases where having the processor read the data as a 24-bit word instead of a 22-bit word is more convenient, the entire register can be mapped to the input level as shown in Figure 51.

Figure 51. 24-Bit Word
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
24-Bit ADC Code, MSB to LSB

Table 4 shows the mapping of the input voltage to the ADC to its output code when the entire 24-bit word is considered.

Table 4. Input Voltage Mapping

DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT 24-BIT ADC OUTPUT CODE
–1.2 V 111000000000000000000000
(–1.2 / 221) V 111111111111111111111111
0 000000000000000000000000
(1.2 / 221) V 000000000000000000000001
1.2 V 000111111111111111111111

Now the data can be considered as a 24-bit data in binary twos complement format, MSB-first. The advantage of using the entire 24-bit word is that the ADC output is correct, even when the input is over the normal operating range.

8.4.1.1 Operation

The ADC digital samples are accumulated and averaged after every 50 µs. Then, at the next rising edge of the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see Figure 52):

  • At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.
  • At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.
  • At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.
  • At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

The number of samples to be used per conversion phase is preset to 2.

ai_tim_adc_data_avg_enable_bas602.gif
NOTE: This example shows three data averages.
Figure 52. ADC Data with Averaging

8.4.2 Diagnostics

The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current profile feedback, and cable on or off detection.

8.4.2.1 Photodiode-Side Fault Detection

Figure 53 shows the diagnostic for the photodiode-side fault detection.

ai_pd_diagnostic_bas601.gifFigure 53. Photodiode Diagnostic

8.4.2.2 Transmitter-Side Fault Detection

Figure 54 shows the diagnostic for the transmitter-side fault detection.

ai_tx_diagnostic_bas601.gifFigure 54. Transmitter Diagnostic

8.4.2.3 Diagnostics Module

The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are latched in 11 separate flags.

At the end of the sequence, the state of the 11 flags are combined to generate two interrupt signals: PD_ALM for photodiode-related faults and LED_ALM for transmit-related faults.

The status of all flags can also be read using the SPI interface. Table 5 details each fault and flag used. Note that the diagnostics module requires all AFE blocks to be enabled in order to function reliably.

Table 5. Fault and Flag Diagnostics(1)

MODULE SEQ. FAULT FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 FLAG10 FLAG11
No fault 0 0 0 0 0 0 0 0 0 0 0
PD 1 Rx INP cable shorted to LED cable 1
2 Rx INN cable shorted to LED cable 1
3 Rx INP cable shorted to GND cable 1
4 Rx INN cable shorted to GND cable 1
5 PD open or shorted 1 1
LED 6 Tx OUTM line shorted to GND cable 1
7 Tx OUTP line shorted to GND cable 1
8 LED open or shorted 1 1
9 LED open or shorted 1
(1) Resistances below 10 kΩ are considered to be shorted.

Figure 55 shows the timing for the diagnostic function.

ai_tim_diagnostic_bas602.gifFigure 55. Diagnostic Timing Diagram

By default, the diagnostic function takes tDIAG = 16 ms to complete. After the diagnostics function completes, the AFE4400 filter must be allowed time to settle. See the Electrical Characteristics for the filter settling time.

8.5 Programming

8.5.1 Serial Programming Interface

The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).

The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts out data from the device. SCLK features a Schmitt-triggered input and clocks data out on the SPISOMI. Data are clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low.

The SPI serial out master in (SPISOMI) pin is used with SCLK to clock out the AFE4400 data. The SPI serial in master out (SPISIMO) pin is used with SCLK to clock in data to the AFE4400. The SPI serial interface enable (SPISTE) pin enables the serial interface to clock data on the SPISIMO pin in to the device.

8.5.2 Reading and Writing Data

The device has a set of internal registers that can be accessed by the serial programming interface formed by the SPISTE, SCLK, SPISIMO, and SPISOMI pins.

8.5.2.1 Writing Data

The SPI_READ register bit must be first set to 0 before writing to a register. When SPISTE is low:

  • Serially shifting bits into the device is enabled.
  • Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
  • The serial data are loaded into the register at every 32nd SCLK rising edge.

In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and the remaining 24 bits form the register data. Figure 56 shows an SPI timing diagram for a single write operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.

ai_tim_afe_spi_wr_bas602.gifFigure 56. AFE SPI Write Timing Diagram

8.5.2.2 Reading Data

The SPI_READ register bit must be first set to 1 before reading from a register. The AFE4400 includes a mode where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. Figure 57 shows an SPI timing diagram for a single read operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.

ai_tim_afe_spi_rd_bas602.gif
1. The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.
2. Specify the register address of the content that must be readback on bits A[7:0].
3. The AFE outputs the contents of the specified register on the SPISOMI pin.
Figure 57. AFE SPI Read Timing Diagram

8.5.2.3 Multiple Data Reads and Writes

The device includes functionality where multiple read and write operations can be performed during a single SPISTE event. To enable this functionality, the first eight bits determine the register address to be written and the remaining 24 bits determine the register data. Perform two writes with the SPI read bit enabled during the second write operation in order to prepare for the read operation, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. This functionality is described in the Writing Data and Reading Data sections. Figure 58 shows a timing diagram for the SPI multiple read and write operations.

ai_tim_serial_multi_rd_wr_ops_bas601.gif
1. The SPI read register bit must be enabled before attempting a serial readout from the AFE.
2. The second write operation must be configured for register 0 with data 000001h.
3. Specify the register address whose contents must be read back on A[7:0].
4. The AFE outputs the contents of the specified register on the SPISOMI pin.
Figure 58. Serial Multiple Read and Write Operations

8.5.2.4 Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be done in one of two ways:

  • Through a hardware reset by applying a low-going pulse on the RESET pin, or
  • By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets to 0. In this case, the RESET pin is kept high (inactive).

8.5.2.5 AFE SPI Interface Design Considerations

Note that when the AFE4400 is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account when connecting multiple devices to the SPI port and for power-management considerations. In order to avoid loading the SPI bus when multiple devices are connected, the DIGOUT_TRISTATE register bit must be to 1 whenever the AFE SPI is inactive.

8.6 Register Maps

8.6.1 AFE Register Map

The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 6. These registers can be accessed using the AFE SPI interface.

Table 6. AFE Register Map

NAME REGISTER CONTROL(1) ADDRESS REGISTER DATA
Hex Dec 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONTROL0 W 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_RST DIAG_EN TIM_COUNT_RST SPI_READ
LED2STC R/W 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0]
LED2ENDC R/W 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0]
LED2LEDSTC R/W 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
LED2LEDENDC R/W 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
ALED2STC R/W 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0]
ALED2ENDC R/W 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
LED1STC R/W 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0]
LED1ENDC R/W 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0]
LED1LEDSTC R/W 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
LED1LEDENDC R/W 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
ALED1STC R/W 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0]
ALED1ENDC R/W 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
LED2CONVST R/W 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0]
LED2CONVEND R/W 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0]
ALED2CONVST R/W 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
ALED2CONVEND R/W 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
LED1CONVST R/W 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0]
LED1CONVEND R/W 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
ALED1CONVST R/W 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
ALED1CONVEND R/W 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
ADCRSTSTCT0 R/W 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0]
ADCRSTENDCT0 R/W 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0]
ADCRSTSTCT1 R/W 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0]
ADCRSTENDCT1 R/W 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0]
ADCRSTSTCT2 R/W 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0]
ADCRSTENDCT2 R/W 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0]
ADCRSTSTCT3 R/W 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0]
ADCRSTENDCT3 R/W 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0]
PRPCOUNT R/W 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0]
CONTROL1 R/W 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 CLKALMPIN[2:0] TIMEREN 0 0 0 0 0 0 1 0
SPARE1 N/A 1F 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIAGAIN R/W 20 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIA_AMB_GAIN R/W 21 33 0 0 0 0 AMBDAC[3:0] 0 STAGE2EN 0 0 0 STG2GAIN[2:0] CF_LED[4:0] RF_LED[2:0]
LEDCNTRL R/W 22 34 0 0 0 0 0 0 LEDCUROFF 1 LED1[7:0] LED2[7:0]
CONTROL2 R/W 23 35 0 0 0 0 0 0 1 0 0 0 0 0 TXBRGMOD DIGOUT_TRISTATE XTALDIS 1 0 0 0 0 0 PDNTX PDNRX PDNAFE
SPARE2 N/A 24 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE3 N/A 25 37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE4 N/A 26 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED1 N/A 27 39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED2 N/A 28 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ALARM R/W 29 41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALMPINCLKEN 0 0 0 0 0 0 0
LED2VAL R 2A 42 LED2VAL[23:0]
ALED2VAL R 2B 43 ALED2VAL[23:0]
LED1VAL R 2C 44 LED1VAL[23:0]
ALED1VAL R 2D 45 ALED1VAL[23:0]
LED2-ALED2VAL R 2E 46 LED2-ALED2VAL[23:0]
LED1-ALED1VAL R 2F 47 LED1-ALED1VAL[23:0]
DIAG R 30 48 0 0 0 0 0 0 0 0 0 0 0 PD_ALM LED_ALM LED1OPEN LED2OPEN LEDSC OUTPSHGND OUTNSHGND PDOC PDSC INNSCGND INPSCGND INNSCLED INPSCLED
(1) R = read only, R/W = read or write, N/A = not available, and W = write only.

8.6.2 AFE Register Description

Figure 59. CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 SW_RST DIAG_EN TIM_
COUNT_
RST
SPI_
READ

This register is write-only. CONTROL0 is used for AFE software and count timer reset, diagnostics enable, and SPI read functions.

Bits 23:4 Must be 0
Bit 3 SW_RST: Software reset
0 = No action (default after reset)
1 = Software reset applied; resets all internal registers to the default values and self-clears to 0
Bit 2 DIAG_EN: Diagnostic enable
0 = No action (default after reset)
1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set.
At the end of the sequence, all fault status are stored in the DIAG: Diagnostics Flag Register. Afterwards, the DIAG_EN register bit self-clears to 0.
Note that the diagnostics enable bit is automatically reset after the diagnostics completes (16 ms). During the diagnostics mode, ADC data are invalid because of the toggling diagnostics switches.
Bit 1 TIM_CNT_RST: Timer counter reset
0 = Disables timer counter reset, required for normal timer operation (default after reset)
1 = Timer counters are in reset state
Bit 0 SPI READ: SPI read
0 = SPI read is disabled (default after reset)
1 = SPI read is enabled
Figure 60. LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2STC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2STC[15:0]

This register sets the start timing value for the LED2 signal sample.

Bits 23:16 Must be 0
Bits 15:0 LED2STC[15:0]: Sample LED2 start count
The contents of this register can be used to position the start of the sample LED2 signal with respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The count is specified as the number of
4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 61. LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2ENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2ENDC[15:0]

This register sets the end timing value for the LED2 signal sample.

Bits 23:16 Must be 0
Bits 15:0 LED2ENDC[15:0]: Sample LED2 end count
The contents of this register can be used to position the end of the sample LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 62. LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2LEDSTC[15:0]

This register sets the start timing value for when the LED2 signal turns on.

Bits 23:16 Must be 0
Bits 15:0 LED2LEDSTC[15:0]: LED2 start count
The contents of this register can be used to position the start of the LED2 with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 63. LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2LEDENDC[15:0]

This register sets the end timing value for when the LED2 signal turns off.

Bits 23:16 Must be 0
Bits 15:0 LED2LEDENDC[15:0]: LED2 end count
The contents of this register can be used to position the end of the LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 64. ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED2STC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED2STC[15:0]

This register sets the start timing value for the ambient LED2 signal sample.

Bits 23:16 Must be 0
Bits 15:0 ALED2STC[15:0]: Sample ambient LED2 start count
The contents of this register can be used to position the start of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 65. ALED2ENDC: Sample Ambient LED2 End Count Register
(Address = 06h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED2ENDC[15:0]

This register sets the end timing value for the ambient LED2 signal sample.

Bits 23:16 Must be 0
Bits 15:0 ALED2ENDC[15:0]: Sample ambient LED2 end count
The contents of this register can be used to position the end of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 66. LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED1STC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1STC[15:0]

This register sets the start timing value for the LED1 signal sample.

Bits 23:17 Must be 0
Bits 16:0 LED1STC[15:0]: Sample LED1 start count
The contents of this register can be used to position the start of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of
4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 67. LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED1ENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1ENDC[15:0]

This register sets the end timing value for the LED1 signal sample.

Bits 23:17 Must be 0
Bits 16:0 LED1ENDC[15:0]: Sample LED1 end count
The contents of this register can be used to position the end of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of
4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 68. LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1LEDSTC[15:0]

This register sets the start timing value for when the LED1 signal turns on.

Bits 23:16 Must be 0
Bits 15:0 LED1LEDSTC[15:0]: LED1 start count
The contents of this register can be used to position the start of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 69. LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1LEDENDC[15:0]

This register sets the end timing value for when the LED1 signal turns off.

Bits 23:16 Must be 0
Bits 15:0 LED1LEDENDC[15:0]: LED1 end count
The contents of this register can be used to position the end of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 70. ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED1STC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED1STC[15:0]

This register sets the start timing value for the ambient LED1 signal sample.

Bits 23:16 Must be 0
Bits 15:0 ALED1STC[15:0]: Sample ambient LED1 start count
The contents of this register can be used to position the start of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 71. ALED1ENDC: Sample Ambient LED1 End Count Register
(Address = 0Ch, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED1ENDC[15:0]

This register sets the end timing value for the ambient LED1 signal sample.

Bits 23:16 Must be 0
Bits 15:0 ALED1ENDC[15:0]: Sample ambient LED1 end count
The contents of this register can be used to position the end of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 72. LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2CONVST[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2CONVST[15:0]

This register sets the start timing value for the LED2 conversion.

Bits 23:16 Must be 0
Bits 15:0 LED2CONVST[15:0]: LED2 convert start count
The contents of this register can be used to position the start of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 73. LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2CONVEND[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2CONVEND[15:0]

This register sets the end timing value for the LED2 conversion.

Bits 23:16 Must be 0
Bits 15:0 LED2CONVEND[15:0]: LED2 convert end count
The contents of this register can be used to position the end of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 74. ALED2CONVST: LED2 Ambient Convert Start Count Register
(Address = 0Fh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED2CONVST[15:0]

This register sets the start timing value for the ambient LED2 conversion.

Bits 23:16 Must be 0
Bits 15:0 ALED2CONVST[15:0]: LED2 ambient convert start count
The contents of this register can be used to position the start of the LED2 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 75. ALED2CONVEND: LED2 Ambient Convert End Count Register
(Address = 10h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED2CONVEND[15:0]

This register sets the end timing value for the ambient LED2 conversion.

Bits 23:16 Must be 0
Bits 15:0 ALED2CONVEND[15:0]: LED2 ambient convert end count
The contents of this register can be used to position the end of the LED2 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 76. LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED1CONVST[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1CONVST[15:0]

This register sets the start timing value for the LED1 conversion.

Bits 23:16 Must be 0
Bits 15:0 LED1CONVST[15:0]: LED1 convert start count
The contents of this register can be used to position the start of the LED1 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 77. LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1CONVEND[15:0]

This register sets the end timing value for the LED1 conversion.

Bits 23:16 Must be 0
Bits 15:0 LED1CONVEND[15:0]: LED1 convert end count
The contents of this register can be used to position the end of the LED1 conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 78. ALED1CONVST: LED1 Ambient Convert Start Count Register
(Address = 13h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED1CONVST[15:0]

This register sets the start timing value for the ambient LED1 conversion.

Bits 23:16 Must be 0
Bits 15:0 ALED1CONVST[15:0]: LED1 ambient convert start count
The contents of this register can be used to position the start of the LED1 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 79. ALED1CONVEND: LED1 Ambient Convert End Count Register
(Address = 14h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED1CONVEND[15:0]

This register sets the end timing value for the ambient LED1 conversion.

Bits 23:16 Must be 0
Bits 15:0 ALED1CONVEND[15:0]: LED1 ambient convert end count
The contents of this register can be used to position the end of the LED1 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 80. ADCRSTSTCT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTSTCT0[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTSTCT0[15:0]

This register sets the start position of the ADC0 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTSTCT0[15:0]: ADC RESET 0 start count
The contents of this register can be used to position the start of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details.
Figure 81. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTENDCT0[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTENDCT0[15:0]

This register sets the end position of the ADC0 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTENDCT0[15:0]: ADC RESET 0 end count
The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details.
Figure 82. ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTSTCT1[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTSTCT1[15:0]

This register sets the start position of the ADC1 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTSTCT1[15:0]: ADC RESET 1 start count
The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 83. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTENDCT1[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTENDCT1[15:0]

This register sets the end position of the ADC1 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTENDCT1[15:0]: ADC RESET 1 end count
The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 84. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTSTCT2[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTSTCT2[15:0]

This register sets the start position of the ADC2 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTSTCT2[15:0]: ADC RESET 2 start count
The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 85. ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTENDCT2[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTENDCT2[15:0]

This register sets the end position of the ADC2 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTENDCT2[15:0]: ADC RESET 2 end count
The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 86. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTSTCT3[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTSTCT3[15:0]

This register sets the start position of the ADC3 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTSTCT3[15:0]: ADC RESET 3 start count
The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 87. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ADCRSTENDCT3[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
ADCRSTENDCT3[15:0]

This register sets the end position of the ADC3 reset conversion signal.

Bits 23:16 Must be 0
Bits 15:0 ADCRSTENDCT3[15:0]: ADC RESET 3 end count
The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details.
Figure 88. PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 PRPCOUNT[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
PRPCOUNT[15:0]

This register sets the device pulse repetition period count.

Bits 23:16 Must be 0
Bits 15:0 PRPCOUNT[15:0]: Pulse repetition period count
The contents of this register can be used to set the pulse repetition period (in number of clock cycles of the 4-MHz clock). The PRPCOUNT value must be set in the range of 800 to 64000. Values below 800 do not allow sufficient sample time for the four samples; see the Electrical Characteristics table.
Figure 89. CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
CLKALMPIN[2:0] TIMEREN 0 0 0 0 0 0 1 0

This register configures the clock alarm pin and timer.

Bits 23:12 Must be 0
Bits 11:9 CLKALMPIN[2:0]: Clocks on ALM pins
Internal clocks can be brought to the PD_ALM and LED_ALM pins for monitoring.
Note that the ALMPINCLKEN register bit must be set before using this register bit. Table 7 defines the settings for the two alarm pins.
Bit 8 TIMEREN: Timer enable
0 = Timer module is disabled and all internal clocks are off (default after reset)
1 = Timer module is enabled
Bits 7:2 Must be 0
Bit 1 Must be 1
Bit 0 Must be 0

Table 7. PD_ALM and LED_ALM Pin Settings

CLKALMPIN[2:0] PD_ALM PIN SIGNAL LED_ALM PIN SIGNAL
000 Sample LED2 pulse Sample LED1 pulse
001 LED2 LED pulse LED1 LED pulse
010 Sample LED2 ambient pulse Sample LED1 ambient pulse
011 LED2 convert LED1 convert
100 LED2 ambient convert LED1 ambient convert
101 No output No output
110 No output No output
111 No output No output
Figure 90. SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0
Figure 91. TIAGAIN: Transimpedance Amplifier Gain Setting Register
(Address = 20h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0

This register is reserved for factory use.

Bits 23:0 Must be 0
Figure 92. TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register (Address = 21h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 AMBDAC[3:0] 0 STAGE2EN 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 STG2GAIN[2:0] CF_LED2[4:0] RF_LED2[2:0]

This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner frequency.

Bits 23:20 Must be 0
Bits 19:16 AMBDAC[3:0]: Ambient DAC value
These bits set the value of the cancellation current.
0000 = 0 µA (default after reset)
0001 = 1 µA
0010 = 2 µA
0011 = 3 µA
0100 = 4 µA
0101 = 5 µA
0110 = 6 µA
0111 = 7 µA
1000 = 8 µA
1001 = 9 µA
1010 = 10 µA
1011 = Do not use
1100 = Do not use
1101 = Do not use
1110 = Do not use
1111 = Do not use
Bit 15 Must be 0
Bit 14 STAGE2EN: Stage 2 enable for LED 2
0 = Stage 2 is bypassed (default after reset)
1 = Stage 2 is enabled with the gain value specified by the STG2GAIN[2:0] bits
Bits 13:11 Must be 0
Bits 10:8 STG2GAIN[2:0]: Stage 2 gain setting
000 = 0 dB, or linear gain of 1 (default after reset)
001 = 3.5 dB, or linear gain of 1.5
010 = 6 dB, or linear gain of 2
011 = 9.5 dB, or linear gain of 3
100 = 12 dB, or linear gain of 4
101 = Do not use
110 = Do not use
111 = Do not use
Bits 7:3 CF_LED[4:0]: Program CF for LEDs
00000 = 5 pF (default after reset)
00001 = 5 pF + 5 pF
00010 = 15 pF + 5 pF
00100 = 25 pF + 5 pF
01000 = 50 pF + 5 pF
10000 = 150 pF + 5 pF
Note that any combination of these CF settings is also supported by setting multiple bits to 1. For example, to obtain CF = 100 pF, set D[7:3] = 01111.
Bits 2:0 RF_LED[2:0]: Program RF for LEDs
000 = 500 kΩ
001 = 250 kΩ
010 = 100 kΩ
011 = 50 kΩ
100 = 25 kΩ
101 = 10 kΩ
110 = 1 MΩ
111 = None
Figure 93. LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 LEDCUROFF 1 LED1[7:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1[7:0] LED2[7:0]

This register sets the LED current range and the LED1 and LED2 drive current.

Bits 23:18 Must be 0
Bit 17 LEDCUROFF: Turns the LED current source on or off
0 = On (50 mA)
1 = Off
Bit 16 Must be 1
Bits 15:8 LED1[7:0]: Program LED current for LED1 signal
Use these register bits to specify the LED current setting for LED1 (default after reset is 00h).
The nominal value of the LED current is given by Equation 3, where the full-scale LED current is 50 mA.
Bits 7:0 LED2[7:0]: Program LED current for LED2 signal
Use these register bits to specify the LED current setting for LED2 (default after reset is 00h).
The nominal value of LED current is given by Equation 4, where the full-scale LED current is 50 mA.
Equation 3. q_led1_bas602.gif
Equation 4. q_led2_bas602.gif
Figure 94. CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 1 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
TXBRG
MOD
DIGOUT_
TRI
STATE
XTAL
DIS
1 0 0 0 0 0 PDNTX PDNRX PDNAFE

This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.

Bits 23:18 Must be 0
Bit 17 Must be 1
Bits 16:12 Must be 0
Bit 11 TXBRGMOD: Tx bridge mode
0 = LED driver is configured as an H-bridge (default after reset)
1 = LED driver is configured as a push-pull
Bit 10 DIGOUT_TRISTATE: Digital output 3-state mode
This bit determines the state of the device digital output pins, including the clock output pin and SPI output pins. In order to avoid loading the SPI bus when multiple devices are connected, this bit must be set to 1 (3-state mode) whenever the device SPI is inactive.
0 = Normal operation (default)
1 = 3-state mode
Bit 9 XTALDIS: Crystal disable mode
0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and XOUT pins
1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin
Bit 8 Must be 1
Bits 7:3 Must be 0
Bit 2 PDN_TX: Tx power-down
0 = The Tx is powered up (default after reset)
1 = Only the Tx module is powered down
Bit 1 PDN_RX: Rx power-down
0 = The Rx is powered up (default after reset)
1 = Only the Rx module is powered down
Bit 0 PDN_AFE: AFE power-down
0 = The AFE is powered up (default after reset)
1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks)
Figure 95. SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0
Figure 96. SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0
Figure 97. SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0
Figure 98. RESERVED1: RESERVED1 Register For Factory Use Only
(Address = 27h, Reset Value = XXXXh)
23 22 21 20 19 18 17 16 15 14 13 12
X(1) X X X X X X X X X X X
11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X
(1) X = don't care.

This register is reserved for factory use. Readback values vary between devices.

Figure 99. RESERVED2: RESERVED2 Register For Factory Use Only
(Address = 28h, Reset Value = XXXXh)
23 22 21 20 19 18 17 16 15 14 13 12
X(1) X X X X X X X X X X X
11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X

This register is reserved for factory use. Readback values vary between devices.

Figure 100. ALARM: Alarm Register (Address = 29h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 ALMPIN
CLKEN
0 0 0 0 0 0 0

This register controls the alarm pin functionality.

Bits 23:8 Must be 0
Bit 7 ALMPINCLKEN: Alarm pin clock enable
0 = Disables the monitoring of internal clocks; the PD_ALM and LED_ALM pins function as diagnostic fault alarm output pins (default after reset)
1 = Enables the monitoring of internal clocks; these clocks can be brought out on PD_ALM and LED_ALM selectively (depending on the value of the CLKALMPIN[2:0] register bits).
Bits 6:0 Must be 0
Figure 101. LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
LED2VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2VAL[23:0]
Bits 23:0 LED2VAL[23:0]: LED2 digital value
This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE.
Figure 102. ALED2VAL: Ambient LED2 Digital Sample Value Register
(Address = 2Bh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
ALED2VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED2VAL[23:0]
Bits 23:0 ALED2VAL[23:0]: LED2 ambient digital value
This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE.
Figure 103. LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
LED1VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1VAL[23:0]
Bits 23:0 LED1VAL[23:0]: LED1 digital value
This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE.
Figure 104. ALED1VAL: Ambient LED1 Digital Sample Value Register
(Address = 2Dh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
ALED1VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
ALED1VAL[23:0]
Bits 23:0 ALED1VAL[23:0]: LED1 ambient digital value
This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE.
Figure 105. LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register
(Address = 2Eh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
LED2-ALED2VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2-ALED2VAL[23:0]
Bits 23:0 LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value
This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host processor must readout this register before the next sample is converted by the AFE.
Note that this value is inverted when compared to waveforms shown in many publications.
Figure 106. LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register
(Address = 2Fh, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
LED1-ALED1VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1-ALED1VAL[23:0]
Bits 23:0 LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value
This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted from it. The host processor must readout this register before the next sample is converted by the AFE.
Note that this value is inverted when compared to waveforms shown in many publications.
Figure 107. DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 PD_ALM
11 10 9 8 7 6 5 4 3 2 1 0
LED_
ALM
LED1
OPEN
LED2
OPEN
LEDSC OUTPSHGND OUTNSHGND PDOC PDSC INNSC
GND
INPSC
GND
INNSC
LED
INPSC
LED

This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.

Bits 23:13 Read only
Bit 12 PD_ALM: Power-down alarm status diagnostic flag
This bit indicates the status of PD_ALM (and the PD_ALM pin).
0 = No fault (default after reset)
1 = Fault present
Bit 11 LED_ALM: LED alarm status diagnostic flag
This bit indicates the status of LED_ALM (and the LED_ALM pin).
0 = No fault (default after reset)
1 = Fault present
Bit 10 LED1OPEN: LED1 open diagnostic flag
This bit indicates that LED1 is open.
0 = No fault (default after reset)
1 = Fault present
Bit 9 LED2OPEN: LED2 open diagnostic flag
This bit indicates that LED2 is open.
0 = No fault (default after reset)
1 = Fault present
This bit indicates that LED2 is open.
0 = No fault (default after reset)
1 = Fault present
Bit 8 LEDSC: LED short diagnostic flag
This bit indicates an LED short.
0 = No fault (default after reset)
1 = Fault present
Bit 7 OUTPSHGND: OUTP to GND diagnostic flag
This bit indicates that OUTP is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 6 OUTNSHGND: OUTN to GND diagnostic flag
This bit indicates that OUTN is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 5 PDOC: PD open diagnostic flag
This bit indicates that PD is open.
0 = No fault (default after reset)
1 = Fault present
Bit 4 PDSC: PD short diagnostic flag
This bit indicates a PD short.
0 = No fault (default after reset)
1 = Fault present
Bit 3 INNSCGND: INN to GND diagnostic flag
This bit indicates a short from the INN pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 2 INPSCGND: INP to GND diagnostic flag
This bit indicates a short from the INP pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 1 INNSCLED: INN to LED diagnostic flag
This bit indicates a short from the INN pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
Bit 0 INPSCLED: INP to LED diagnostic flag
This bit indicates a short from the INP pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present