Table 7-31 Switching Characteristics for LPDDR Memory Interface

7.7.2.1.2.1 LPDDR Interface Schematic

Figure 7-33 shows the schematic connections for 16-bit interface on the AM335x device using one x16 LPDDR device. The AM335x LPDDR memory interface only supports 16-bit-wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and one load connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 7.7.2.1.2.8.

A. Enable internal weak pulldown on these pins. For details, see the EMIF section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.

B. For all the termination requirements, see Section 7.7.2.1.2.9.

Figure 7-33 16-Bit LPDDR Interface Using One 16-Bit LPDDR Device

7.7.2.1.2.2 Compatible JEDEC LPDDR Devices

Table 7-32 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface. Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices.

1. If the LPDDR interface is operated with a clock frequency less than 200 MHz, lower-speed grade LPDDR devices may be used if the minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the AM335x LPDDR interface.

7.7.2.1.2.3 PCB Stackup

The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-33. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

1. All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross splits in the power plane.

Complete stackup specifications are provided in Table 7-34.

1. For the LPDDR device BGA pad size, see the LPDDR device manufacturer documentation.
2. A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to the AM335x device.
3. Zo is the nominal singled-ended impedance selected for the PCB.
4. This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter.
5. Tighter impedance control is required to ensure flight time skew is minimal.

7.7.2.1.2.4 Placement

Figure 7-34 shows the required placement for the LPDDR devices. The dimensions for this figure are defined in Table 7-35. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory LPDDR systems, the second LPDDR device is omitted from the placement.

Figure 7-34 AM335x Device and LPDDR Device Placement

1. LPDDR keepout region to encompass entire LPDDR routing area.
2. For dimension definitions, see Figure 7-34.
3. Measurements from center of the AM335x device to center of LPDDR device.
4. For single-memory systems, TI recommends that Y offset be as small as possible.
5. w is defined as the signal trace width.
6. Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.

7.7.2.1.2.5 LPDDR Keepout Region

The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keepout region is defined for this purpose and is shown in Figure 7-35. This region should encompass all LPDDR circuitry and the region size varies with component placement and LPDDR routing. Additional clearances required for the keepout region are shown in Table 7-35. Non-LPDDR signals must not be routed on the same signal layer as LPDDR signals within the LPDDR keepout region. Non-LPDDR signals may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region.

Figure 7-35 LPDDR Keepout Region

7.7.2.1.2.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry. Table 7-36 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x LPDDR interface and LPDDR devices. Additional bulk bypass capacitance may be needed for other circuitry.

1. These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass capacitors.
2. Only used when two LPDDR devices are used.

7.7.2.1.2.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device LPDDR power, and the AM335x device LPDDR ground connections. Table 7-37 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.

1. LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
2. An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
3. These devices should be placed as close as possible to the device being bypassed.
4. Per LPDDR device.

7.7.2.1.2.8 Net Classes

Table 7-38 lists the clock net classes for the LPDDR interface. Table 7-39 lists the signal net classes, and associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the termination and routing rules that follow.

7.7.2.1.2.9 LPDDR Signal Termination

There is no specific need for adding terminations on the LPDDR interface. However, system designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device. Table 7-40 shows the specifications for the serial terminators in such cases.

1. Only series termination is permitted.
2. Zo is the LPDDR PCB trace characteristic impedance.
3. Series termination values larger than typical only recommended to address EMI issues.
4. Series termination values should be uniform across net class.

Table 7-41 CK and ADDR_CTRL Routing Specification⁽¹⁾⁽²⁾

Table 7-42 DQS[x] and DQ[x] Routing Specification⁽¹⁾

Table 7-43 Switching Characteristics for DDR2 Memory Interface

7.7.2.2.2.1 DDR2 Interface Schematic

Figure 7-39 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR2 device and Figure 7-40 shows the schematic connections for 16-bit interface on the AM335x device using two x8 DDR2 devices. The AM335x DDR2 memory interface only supports 16-bit-wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 7.7.2.2.2.8.

A. VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin.

C. For all the termination requirements, see Section 7.7.2.2.2.9.

Figure 7-39 16-Bit DDR2 Interface Using One 16-Bit DDR2 Device

A. VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin.

C. For all the termination requirements, see Section 7.7.2.2.2.9.

Figure 7-40 16-Bit DDR2 Interface Using Two 8-Bit DDR2 Devices

7.7.2.2.2.2 Compatible JEDEC DDR2 Devices

Table 7-44 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface. Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices.

1. If the DDR2 interface is operated with a clock frequency less than 266 MHz, lower-speed grade DDR2 devices may be used if the minimum clock period specified for the DDR2 device is less than or equal to the minimum clock period selected for the AM335x DDR2 interface.
2. Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backward compatibility.
3. 92-terminal devices are also supported for legacy reasons. New designs will migrate to 84-terminal DDR2 devices. Electrically, the 92- and 84-terminal DDR2 devices are the same.

7.7.2.2.2.3 PCB Stackup

The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-45. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

1. All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross splits in the power plane.

Complete stackup specifications are provided in Table 7-46.

1. For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation.
2. A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to the AM335x device.
3. Zo is the nominal singled-ended impedance selected for the PCB.
4. This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter.
5. Tighter impedance control is required to ensure flight time skew is minimal.

7.7.2.2.2.4 Placement

Figure 7-41 shows the required placement for the DDR2 devices. The dimensions for this figure are defined in Table 7-47. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement.

Figure 7-41 AM335x Device and DDR2 Device Placement

1. DDR2 keepout region to encompass entire DDR2 routing area.
2. For dimension definitions, see Figure 7-41.
3. Measurements from center of the AM335x device to center of the DDR2 device.
4. For single-memory systems, it is recommended that Y offset be as small as possible.
5. w is defined as the signal trace width.
6. Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

7.7.2.2.2.5 DDR2 Keepout Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keepout region is defined for this purpose and is shown in Figure 7-42. This region should encompass all DDR2 circuitry and the region size varies with component placement and DDR2 routing. Additional clearances required for the keepout region are shown in Table 7-47. Non-DDR2 signals must not be routed on the same signal layer as DDR2 signals within the DDR2 keepout region. Non-DDR2 signals may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region.

Figure 7-42 DDR2 Keepout Region

7.7.2.2.2.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 7-48 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x DDR2 interface and DDR2 devices. Additional bulk bypass capacitance may be needed for other circuitry.

1. These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass capacitors.
2. Only used when two DDR2 devices are used.

7.7.2.2.2.7 High-Speed (HS) Bypass Capacitors

HS bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR2 power, and the AM335x device DDR2 ground connections. Table 7-49 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.

1. LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
2. An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
3. These devices should be placed as close as possible to the device being bypassed.
4. Per DDR2 device.

7.7.2.2.2.8 Net Classes

Table 7-50 lists the clock net classes for the DDR2 interface. Table 7-51 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the termination and routing rules that follow.

7.7.2.2.2.9 DDR2 Signal Termination

Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to ensure signal integrity. Table 7-52 shows the specifications for the series terminators. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device.

1. Only series termination is permitted.
2. Series termination values larger than typical only recommended to address EMI issues.
3. Series termination values should be uniform across net class.
4. Zo is the DDR2 PCB trace characteristic impedance.
5. No external termination resistors are allowed and ODT must be used for these net classes.

If the DDR2 interface is operated at a lower frequency (<200-MHz clock rate), on-device terminations are not specifically required for the DQS[x] and DQ[x] net class signals and serial terminations for the CK and ADDR_CTRL net class signals are not mandatory. System designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device. Table 7-53 shows the specifications for the serial terminators in such cases.

1. Only series termination is permitted.
2. Zo is the DDR2 PCB trace characteristic impedance.
3. Series termination values larger than typical only recommended to address EMI issues.
4. Series termination values should be uniform across net class.

7.7.2.2.2.10 DDR_VREF Routing

DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 7-39 and Figure 7-40. TI does not recommend other methods of creating DDR_VREF. Figure 7-43 shows the layout guidelines for DDR_VREF.

Figure 7-43 DDR_VREF Routing and Topology

Table 7-54 CK and ADDR_CTRL Routing Specification⁽¹⁾⁽²⁾

Table 7-55 DQS[x] and DQ[x] Routing Specification⁽¹⁾

Table 7-56 Switching Characteristics for DDR3 Memory Interface

7.7.2.3.1.1 DDR3 versus DDR2

This specification only covers AM335x PCB designs that use DDR3 memory. Designs using DDR2 memory should use the DDR2 routing guidleines described in Section 7.7.2.2. While similar, the two memory systems have different requirements. It is currently not possible to design one PCB that meets the requirements of both DDR2 and DDR3.

Table 7-57 Supported DDR3 Device Combinations

7.7.2.3.3.1 DDR3 Interface Schematic

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 7-47 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR3 device and Figure 7-49 shows the schematic connections for 16-bit interface on the AM335x device using two x8 DDR3 devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 7.7.2.3.3.8.

Figure 7-47 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device with V_TT Termination

A. VDDS_DDR is the power supply for the DDR3 memories and the AM335x DDR3 interface.

Figure 7-48 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device without V_TT Termination

Figure 7-49 16-Bit DDR3 Interface Using Two 8-Bit DDR3 Devices

7.7.2.3.3.2 Compatible JEDEC DDR3 Devices

Table 7-58 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

1. For valid DDR3 device configurations and device counts, see Section 7.7.2.3.3.1, Figure 7-47, and Figure 7-49.

7.7.2.3.3.3 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 7-59. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

1. All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross splits in the power plane.

1. For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.
2. Ground reference layers are preferred over power reference layers. Be sure to include bypass capacitors to accommodate reference layer return current as the trace routes switch routing layers.
3. No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation.
4. Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
5. An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape.
6. Zo is the nominal singled-ended impedance selected for the PCB.
7. This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter.
8. Tighter impedance control is required to ensure flight time skew is minimal.

7.7.2.3.3.4 Placement

Figure 7-50 shows the required placement for the AM335x device as well as the DDR3 devices. The dimensions for this figure are defined in Table 7-61. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.

Figure 7-50 Placement Specifications

1. DDR3 keepout region to encompass entire DDR3 routing area.
2. For dimension definitions, see Figure 7-50.
3. Measurements from center of the AM335x device to center of the DDR3 device.
4. Minimizing X1 and Y improves timing margins.
5. w is defined as the signal trace width.
6. Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.

7.7.2.3.3.5 DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 7-51. This region should encompass all DDR3 circuitry and the region size varies with component placement and DDR3 routing. Additional clearances required for the keepout region are shown in Table 7-61. Non-DDR3 signals must not be routed on the same signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in the region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region.

Figure 7-51 DDR3 Keepout Region

7.7.2.3.3.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 7-62 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x DDR3 interface and DDR3 devices. Additional bulk bypass capacitance may be needed for other circuitry.

1. These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass capacitors and DDR3 signal routing.
2. Only used when two DDR3 devices are used.

7.7.2.3.3.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR3 power, and the AM335x device DDR3 ground connections. Table 7-63 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

• Fit as many HS bypass capacitors as possible.
• Minimize the distance from the bypass capacitor to the power terminals being bypassed.
• Use the smallest physical sized capacitors possible with the highest capacitance readily available.
• Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible.
• Minimize via sharing. Note the limits on via sharing shown in Table 7-63.

1. LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
2. Closer and shorter is better.
3. Measured from the nearest AM335x VDDS_DDR and ground terminal to the center of the capacitor package.
4. Three of these capacitors should be located underneath the AM335x device, between the cluster of VDDS_DDR and ground terminals, between the DDR3 interfaces on the package.
5. Measured from the DDR3 device power and ground terminal to the center of the capacitor package.
6. Per DDR3 device.
7. An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
8. An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils.
9. Up to two pairs of DDR3 power and ground terminals may share a via.

7.7.2.3.3.8 Net Classes

Table 7-64 lists the clock net classes for the DDR3 interface. Table 7-65 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination and routing rules that follow.

7.7.2.3.3.9 DDR3 Signal Termination

Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are covered in the routing rules in the following sections.

Figure 7-48 provides an example DDR3 schematic with a single 16-bit DDR3 memory device that does not have V_TT termination on the address and control signals. A typical DDR3 point-to-point topology may provide acceptable signal integrity without V_TT termination. System performance should be verified by performing signal integrity analysis using specific PCB design details before implementing this topology.

7.7.2.3.3.10 DDR_VREF Routing

DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate routing congestion.

7.7.2.3.3.11 VTT

Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.

7.7.2.3.4.1 Two DDR3 Devices

Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices

Figure 7-52 shows the topology of the CK net classes and Figure 7-53 shows the topology for the corresponding ADDR_CTRL net classes.

Figure 7-52 CK Topology for Two DDR3 Devices

Figure 7-53 ADDR_CTRL Topology for Two DDR3 Devices

7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices

Figure 7-54 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 7-55 shows the corresponding ADDR_CTRL routing.

Figure 7-54 CK Routing for Two Single-Sided DDR3 Devices

Figure 7-55 ADDR_CTRL Routing for Two Single-Sided DDR3 Devices

To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 7-56 and Figure 7-57 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration.

Figure 7-56 CK Routing for Two Mirrored DDR3 Devices

Figure 7-57 ADDR_CTRL Routing for Two Mirrored DDR3 Devices

7.7.2.3.4.2 One DDR3 Device

One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16-bit bank.

7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device

Figure 7-58 shows the topology of the CK net classes and Figure 7-59 shows the topology for the corresponding ADDR_CTRL net classes.

Figure 7-58 CK Topology for One DDR3 Device

Figure 7-59 ADDR_CTRL Topology for One DDR3 Device

7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device

Figure 7-60 shows the CK routing for one DDR3 device. Figure 7-61 shows the corresponding ADDR_CTRL routing.

Figure 7-60 CK Routing for One DDR3 Device

Figure 7-61 ADDR_CTRL Routing for One DDR3 Device

7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices

DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point single-ended. Figure 7-62 and Figure 7-63 show these topologies.

x = 0, 1

Figure 7-62 DQS[x] Topology

x = 0, 1

Figure 7-63 DQ[x] Topology

7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices

Figure 7-64 and Figure 7-65 show the DQS[x] and DQ[x] routing.

x = 0, 1

Figure 7-64 DQS[x] Routing With Any Number of Allowed DDR3 Devices

x = 0, 1

Figure 7-65 DQ[x] Routing With Any Number of Allowed DDR3 Devices

7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance.

Given the clock and address pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-66 shows this distance for two loads. The specifications on the lengths of the transmission lines for the address bus are determined from this distance. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 7-66.

A. It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control.

The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Nonincluded lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 7-66 CACLM for Two Address Loads on One Side of PCB

1. CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
2. The use of vias should be minimized.
3. Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump between the VDDS_DDR plane and the ground plane when the net class switches layers at a via.
4. Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
5. Nonmirrored configuration (all DDR3 memories on same side of PCB).
6. While this length can be increased for convenience, its length should be minimized.
7. ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
8. CK net class only.
9. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 7.7.2.3.6.1 and Figure 7-66.
10. Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
11. Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.
12. CK spacing set to ensure proper differential impedance. Differential impedance should be Z_o x 2, where Z_o is the single-ended impedance defined in Table 7-60.
13. Source termination (series resistor at driver) is specifically not allowed.
14. Termination values should be uniform across the net class.

7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification

Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

Given the DQS[x] and DQ[x] pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-67 shows this distance for a two-load case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 7-67.

There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1

Figure 7-67 DQLM for Any Number of Allowed DDR3 Devices

1. DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
2. External termination disallowed. Data termination should use built-in ODT functionality.
3. DQLMn is the longest Manhattan distance of a byte. For definition, see Section 7.7.2.3.6.2 and Figure 7-67.
4. DQLM0 is the longest Manhattan length for the DQ0 net class.
5. DQLM1 is the longest Manhattan length for the DQ1 net class.
6. Length matching is only done within a byte. Length matching across bytes is not required.
7. Each DQS clock net class is length matched to its associated DQ signal net class.
8. Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
9. Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
10. This applies to spacing within same DQ[x] signal net class.
11. DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Z_o x 2, where Z_o is the single-ended impedance defined in Table 7-60.