JAJSD78A May   2017  – May 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 USB On-The-Go (OTG)
      4. 8.3.4 Converter Operation
        1. 8.3.4.1 Inductor Setting through IADPT Pin
        2. 8.3.4.2 Continuous Conduction Mode (CCM)
        3. 8.3.4.3 Pulse Frequency Modulation (PFM)
      5. 8.3.5 Current and Power Monitor
        1. 8.3.5.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.5.2 High-Accuracy Power Sense Amplifier (PSYS)
      6. 8.3.6 Input Source Dynamic Power Manage
      7. 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
      8. 8.3.8 Processor Hot Indication
        1. 8.3.8.1 PROCHOT During Low Power Mode
        2. 8.3.8.2 PROCHOT Status
      9. 8.3.9 Device Protection
        1. 8.3.9.1 Watchdog Timer
        2. 8.3.9.2 Input Overvoltage Protection (ACOV)
        3. 8.3.9.3 Input Overcurrent Protection (ACOC)
        4. 8.3.9.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.9.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.9.6 Battery Short
        7. 8.3.9.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
      2. 8.4.2 USB On-The-Go
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Slave Address and Data Direction Bit
        6. 8.5.1.6 Single Read and Write
        7. 8.5.1.7 Multi-Read and Multi-Write
        8. 8.5.1.8 Write 2-Byte I2C Commands
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E20Eh]
          1. Table 5. ChargeOption0 Register (I2C address = 01h) Field Descriptions
          2. Table 6. ChargeOption0 Register (I2C address = 00h) Field Descriptions
        2. 8.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]
          1. Table 7. ChargeOption1 Register (I2C address = 31h) Field Descriptions
          2. Table 8. ChargeOption1 Register (I2C address = 30h) Field Descriptions
        3. 8.6.1.3 ChargeOption2 Register (I2C address = 33/32h) [reset = 2B7]
          1. Table 9.  ChargeOption2 Register (I2C address = 33h) Field Descriptions
          2. Table 10. ChargeOption2 Register (I2C address = 32h) Field Descriptions
        4. 8.6.1.4 ChargeOption3 Register (I2C address = 35/34h) [reset = 0h]
          1. Table 11. ChargeOption3 Register (I2C address = 35h) Field Descriptions
          2. Table 12. ChargeOption3 Register (I2C address = 34h) Field Descriptions
        5. 8.6.1.5 ProchotOption0 Register (I2C address = 37/36h) [reset = 04A54h]
          1. Table 13. ProchotOption0 Register (I2C address = 37h) Field Descriptions
          2. Table 14. ProchotOption0 Register (I2C address = 36h) Field Descriptions
        6. 8.6.1.6 ProchotOption1 Register (I2C address = 39/38h) [reset = 8120h]
          1. Table 15. ProchotOption1 Register (I2C address = 39h) Field Descriptions
          2. Table 16. ProchotOption1 Register (I2C address = 38h) Field Descriptions
        7. 8.6.1.7 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
          1. Table 17. ADCOption Register (I2C address = 3Bh) Field Descriptions
          2. Table 18. ADCOption Register (I2C address = 3Ah) Field Descriptions
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
          1. Table 19. ChargerStatus Register (I2C address = 21h) Field Descriptions
          2. Table 20. ChargerStatus Register (I2C address = 20h) Field Descriptions
        2. 8.6.2.2 ProchotStatus Register (I2C address = 23/22h) [reset = 0h]
          1. Table 21. ProchotStatus Register (I2C address = 23h) Field Descriptions
          2. Table 22. ProchotStatus Register (I2C address = 22h) Field Descriptions
      3. 8.6.3  ChargeCurrent Register (I2C address = 03/02h) [reset = 0h]
        1. Table 23. Charge Current Register (14h) With 10-mΩ Sense Resistor (I2C address = 03h) Field Descriptions
        2. Table 24. Charge Current Register (14h) With 10-mΩ Sense Resistor (I2C address = 02h) Field Descriptions
        3. 8.6.3.1   Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
        1. Table 25. MaxChargeVoltage Register (I2C address = 05h) Field Descriptions
        2. Table 26. MaxChargeVoltage Register (I2C address = 04h) Field Descriptions
      5. 8.6.5  MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
        1. Table 27. MinSystemVoltage Register (I2C address = 0Dh) Field Descriptions
        2. Table 28. MinSystemVoltage Register (I2C address = 0Ch) Field Descriptions
        3. 8.6.5.1   System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0F/0Eh) [reset = 4000h]
            1. Table 29. IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0Fh) Field Descriptions
            2. Table 30. IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0Eh) Field Descriptions
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (I2C address = 25/24h) [reset = 0h]
            1. Table 31. IIN_DPM Register With 10-mΩ Sense Resistor (I2C address = 25h) Field Descriptions
            2. Table 32. IIN_DPM Register With 10-mΩ Sense Resistor (I2C address = 24h) Field Descriptions
          3. 8.6.6.1.3 InputVoltage Register (I2C address = 0B/0Ah) [reset = VBUS-1.28V]
            1. Table 33. InputVoltage Register (I2C address = 0Bh) Field Descriptions
            2. Table 34. InputVoltage Register (I2C address = 0Ah) Field Descriptions
      7. 8.6.7  OTGVoltage Register (I2C address = 07/06h) [reset = 0h]
        1. Table 35. OTGVoltage Register (I2C address = 07h) Field Descriptions
        2. Table 36. OTGVoltage Register (I2C address = 06h) Field Descriptions
      8. 8.6.8  OTGCurrent Register (I2C address = 09/08h) [reset = 0h]
        1. Table 37. OTGCurrent Register (I2C address = 09h) Field Descriptions
        2. Table 38. OTGCurrent Register (I2C address = 08h) Field Descriptions
      9. 8.6.9  ADCVBUS/PSYS Register (I2C address = 27/26h)
        1. Table 39. ADCVBUS/PSYS Register (I2C address = 27h) Field Descriptions
        2. Table 40. ADCVBUS/PSYS Register (I2C address = 26h) Field Descriptions
      10. 8.6.10 ADCIBAT Register (I2C address = 29/28h)
        1. Table 41. ADCIBAT Register (I2C address = 29h) Field Descriptions
        2. Table 42. ADCIBAT Register (I2C address = 28h) Field Descriptions
      11. 8.6.11 ADCIINCMPIN Register (I2C address = 2B/2Ah)
        1. Table 43. ADCIINCMPIN Register (I2C address = 2Bh) Field Descriptions
        2. Table 44. ADCIINCMPIN Register (I2C address = 2Ah) Field Descriptions
      12. 8.6.12 ADCVSYSVBAT Register (I2C address = 2D/2Ch)
        1. Table 45. ADCVSYSVBAT Register (I2C address = 2Dh) Field Descriptions
        2. Table 46. ADCVSYSVBAT Register (I2C address = 2Ch) Field Descriptions
      13. 8.6.13 ID Registers
        1. 8.6.13.1 ManufactureID Register (I2C address = 2Eh) [reset = 0040h]
          1. Table 47. ManufactureID Register Field Descriptions
        2. 8.6.13.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = 0h]
          1. Table 48. Device ID (DeviceAddress) Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]

Figure 24. ChargeOption1 Register (I2C address = 31/30h) [reset = 211h]
7 6 5 4 3 2 1 0
EN_IBAT EN_PROCHOT_LPWR EN_PSYS RSNS_RAC RSNS_RSR PSYS_RATIO Reserved
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
CMP_REF CMP_POL CMP_DEG FORCE_
LATCHOFF		 Reserved EN_SHIP_
DCHG		 AUTO_
WAKEUP_EN
R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. ChargeOption1 Register (I2C address = 31h) Field Descriptions

I2C
31h		 FIELD TYPE RESET DESCRIPTION
7 EN_IBAT R/W 0b

IBAT Enable

Enable the IBAT output buffer. In low power mode (REG0x01[7] = 1), IBAT buffer is always disabled regardless of this bit value.

0b Turn off IBAT buffer to minimize Iq <default at POR>

1b: Turn on IBAT buffer

6-5 EN_PROCHOT
_LPWR 		R/W 00b

Enable PROCHOT during battery only low power mode

With battery only, enable IDCHG or VSYS in PROCHOT with low power consumption. Do not enable this function with adapter present. Refer to PROCHOT During Low Power Mode for more details.

00b: Disable low power PROCHOT <default at POR>

01b: Enable IDCHG low power PROCHOT

10b: Enable VSYS low power PROCHOT

11b: Reserved
4 EN_PSYS R/W 0b

PSYS Enable

Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low power mode (REG0x01[7] = 1), PSYS sensing and buffer are always disabled regardless of this bit value.

0b: Turn off PSYS buffer to minimize Iq <default at POR>

1b: Turn on PSYS buffer

3 RSNS_RAC R/W 0b

Input sense resistor RAC

0b: 10 mΩ <default at POR>

1b: 20 mΩ
2 RSNS_RSR R/W 0b

Charge sense resistor RSR

0b: 10 mΩ <default at POR>

1b: 20 mΩ
1 PSYS_RATIO R/W 1b

PSYS Gain

Ratio of PSYS output current vs total input and battery power with 10-mΩ sense resistor.

0b: 0.25 µA/W

1b: 1 µA/W <default at POR>
0 Reserved R/W 0b

Reserved

Table 8. ChargeOption1 Register (I2C address = 30h) Field Descriptions

I2C
30h		 FIELD TYPE RESET DESCRIPTION
7 CMP_REF R/W 0b

Independent Comparator Internal Reference.

0b: 2.3 V <default at POR>

1b: 1.2 V

6 CMP_POL R/W 0b

Independent Comparator Output Polarity

0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal hysteresis) <default at POR>

1b: When CMPIN is below internal threshold, CMPOUT is LOW (external hysteresis)
5-4 CMP_DEG R/W 01b

Independent Comparator Deglitch Time, only applied to the falling edge of CMPOUT (HIGH → LOW).

00b: Independent comparator is disabled

01b: Independent comparator is enabled with output deglitch time 1 µs <default at POR>

10b: Independent comparator is enabled with output deglitch time of 2 ms

11b: Independent comparator is enabled with output deglitch time of 5 sec

3 FORCE_LATCHOFF R/W 0b

Force Power Path Off

When independent comparator triggers, charger turns off Q1 and Q4 (same as disable converter) so that the system is disconnected from the input source. At the same time, CHRG_OK signal goes to LOW to notify the system.

0b: Disable this function <default at POR>

1b: Enable this function
2 Reserved R/W 0b

Reserved

1 EN_SHIP_DCHG R/W 0b

Discharge SRN for Shipping Mode

When this bit is 1, discharge SRN pin down below 3.8 V in 140 ms. When 140 ms is over, this bit is reset to 0.

0b: Disable shipping mode <default at POR>

1b: Enable shipping mode

0 AUTO_WAKEUP_EN R/W 1b

Auto Wakeup Enable

When this bit is HIGH, if the battery is below minimum system voltage (REG0x0D/0C()), the device will automatically enable 128 mA charging current for 30 mins. When the battery is charged up above minimum system voltage, charge will terminate and the bit is reset to LOW.

0b: Disable

1b: Enable <default at POR>