JAJSL70A February   2021  – January 2024 BQ25730

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. 概要 (続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics(BQ25730)
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-Up Sequence
      2. 8.3.2  Two-Level Battery Discharge Current Limit
      3. 8.3.3  Fast Role Swap Feature
      4. 8.3.4  CHRG_OK Indicator
      5. 8.3.5  Input and Charge Current Sensing
      6. 8.3.6  Input Voltage and Current Limit Setup
      7. 8.3.7  Battery Cell Configuration
      8. 8.3.8  Device HIZ State
      9. 8.3.9  USB On-The-Go (OTG)
      10. 8.3.10 Converter Operation
      11. 8.3.11 Inductance Detection Through IADPT Pin
      12. 8.3.12 Converter Compensation
      13. 8.3.13 Continuous Conduction Mode (CCM)
      14. 8.3.14 Pulse Frequency Modulation (PFM)
      15. 8.3.15 Switching Frequency and Dithering Feature
      16. 8.3.16 Current and Power Monitor
        1. 8.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)
      17. 8.3.17 Input Source Dynamic Power Management
      18. 8.3.18 Input Current Optimizer (ICO)
      19. 8.3.19 Two-Level Adapter Current Limit (Peak Power Mode)
      20. 8.3.20 Processor Hot Indication
        1. 8.3.20.1 PROCHOT During Low Power Mode
        2. 8.3.20.2 PROCHOT Status
      21. 8.3.21 Device Protection
        1. 8.3.21.1 Watchdog Timer
        2. 8.3.21.2 Input Overvoltage Protection (ACOV)
        3. 8.3.21.3 Input Overcurrent Protection (ACOC)
        4. 8.3.21.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.21.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.21.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 8.3.21.7 Battery Short Protection (BATSP)
        8. 8.3.21.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 8.3.21.9 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
      2. 8.4.2 USB On-The-Go
      3. 8.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
        1. 8.5.1.1 Timing Diagrams
        2. 8.5.1.2 Data Validity
        3. 8.5.1.3 START and STOP Conditions
        4. 8.5.1.4 Byte Format
        5. 8.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 8.5.1.6 Target Address and Data Direction Bit
        7. 8.5.1.7 Single Read and Write
        8. 8.5.1.8 Multi-Read and Multi-Write
        9. 8.5.1.9 Write 2-Byte I2C Commands
    6. 8.6 Register Map
      1. 8.6.1  ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
      2. 8.6.2  ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
        1. 8.6.2.1 Battery Pre-Charge Current Clamp
      3. 8.6.3  ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      4. 8.6.4  ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
      5. 8.6.5  ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
      6. 8.6.6  IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
      7. 8.6.7  ADCVBUS/PSYS Register (I2C address = 27/26h)
      8. 8.6.8  ADCIBAT Register (I2C address = 29/28h)
      9. 8.6.9  ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
      10. 8.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
      11. 8.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]
      12. 8.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
      13. 8.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
      14. 8.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
      15. 8.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
      16. 8.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      17. 8.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
      18. 8.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
      19. 8.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
      20. 8.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
      21. 8.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
      22. 8.6.22 VSYS_MIN Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
      23. 8.6.23 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]
      24. 8.6.24 ID Registers
        1. 8.6.24.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
        2. 8.6.24.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D5h]
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 9.2.2.2 ACP-ACN Input Filter
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Output Capacitor
        6. 9.2.2.6 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Example Reference Top View
      2. 11.2.2 Inner Layer Layout and Routing Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]

Figure 8-19 ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
7 6 5 4 3 2 1 0
STAT_AC ICO_DONE IN_VAP IN_VINDPM IN_IIN_DPM IN_FCHRG IN_PCHRG IN_OTG
R R R R R R R R
7 6 5 4 3 2 1 0
Fault ACOV Fault BATOC Fault ACOC FAULT SYSOVP Fault VSYS _UVP Fault Force_Converter_Off Fault_OTG _OVP Fault_OTG _UVP
R R R R/W R/W R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-14 ChargerStatus Register (I2C address = 21h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 STAT_AC R 0b

Input source status. STAT_AC is valid as long as VBUS go within 3.5-V to 26-V range. It is different from CHRG_OK bit, When CHRG_OK is valid, STAT_AC must be valid, but if STAT_AC is valid, it is not necessary CHRG_OK is valid. There are Force converter off, ACOC, TSHUT , SYSOVP, VSYS_UVP, BATOVP can pull low CHRG_OK.

0b: Input not present

1b: Input is present

6 ICO_DONE R 0b

After the ICO routine is successfully executed, the bit goes 1.

0b: ICO is not complete

1b: ICO is complete

5 IN_VAP R 0b

0b: Charger is not operated in VAP mode

1b: Charger is operated in VAP mode

Digital status bit indicates VAP has enabled(1) or disabled(0). The enable of VAP mode only follows the host command, which is not blocked by any status of /PROCHOT. The exit of VAP mode also follows the host command, except that any faults will exit VAP mode automatically. STAT_EXIT_VAP (REG0x22[8]) becomes 1 which will pull low /PROCHOT until host clear.

The host can enable VAP by setting OTG/VAP/FRS pin high and 0x32[5]=0, disable VAP by setting either OTG/VAP/FRS pin low or 0x32[5]=1. Any faults in VAP When IN_VAP bit goes 0->1, charger should disable VINDPM, IIN_DPM, ICRIT, ILIM pin, disable PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When IN_VAP bit goes 1->0, charger should enable VINDPM, IIN_DPM, ICRIT, ILIM pin function.

4 IN_VINDPM R 0b

0b: Charger is not in VINDPM during forward mode, or voltage regulation during OTG mode

1b: Charger is in VINDPM during forward mode, or voltage regulation during OTG mode

3 IN_IIN_DPM R 0b

0b: Charger is not in IIN_DPM during forward mode.

1b: Charger is in IIN_DPM during forward mode.

2 IN_FCHRG R 0b

0b: Charger is not in fast charge

1b: Charger is in fast charger

1 IN_PCHRG R 0b

0b: Charger is not in pre-charge

1b: Charger is in pre-charge

0 IN_OTG R 0b

0b: Charger is not in OTG

1b: Charge is in OTG

Table 8-15 ChargerStatus Register (I2C address = 20h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 Fault ACOV R 0b

The status are latched if triggered until a read from host.

0b: No fault

1b: ACOV

6 Fault BATOC R 0b

The status is latched if triggered until a read from host. Fault indicator for BATOC only during normal operation. However, in PTM mode when EN_BATOC=1b, this status bit is fault indicator for both BATOVP and BATOC; when EN_BATOC=0b, this status bit is not effective.

0b: No fault

1b: BATOC is triggered

5 Fault ACOC R 0b

The status is latched if triggered until a read from host.

0b: No fault

1b: ACOC

4 Fault SYSOVP R/W 0b

SYSOVP Status and Clear. SYSOVP fault is latched until a clear from host by writing this bit to 0.

When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the converter is disabled.

After the SYSOVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the SYSOVP condition to enable the converter again.

0b: Not in SYSOVP <default at POR>

1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the SYSOVP latch.

3 Fault VSYS_UVP R/W 0b

VSYS_UVP fault status and clear. VSYS_UVP fault is latched until a clear from host by writing this bit to 0.

0b: No fault <default at POR>

1b: When system voltage is lower than VSYS_UVP, then 7 times restart tries are failed.

2 Fault Force_Converter_Off R 0b

The status is latched if triggered until a read from host.

0b: No fault

1b: Force converter off triggered (when FORCE_CONV_OFF (REG0x30[3])=1b)

1 Fault_OTG_OVP R 0b

The status is latched if triggered until a read from host.

0b: No fault

1b: OTG OVP fault is triggered

0 Fault_OTG_UVP R 0b

The status is latched if triggered until a read from host.

0b: No fault

1b: OTG UVP fault is triggered