JAJSL70A February   2021  – January 2024 BQ25730

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics(BQ25730)
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-Up Sequence
      2. 8.3.2  Two-Level Battery Discharge Current Limit
      3. 8.3.3  Fast Role Swap Feature
      4. 8.3.4  CHRG_OK Indicator
      5. 8.3.5  Input and Charge Current Sensing
      6. 8.3.6  Input Voltage and Current Limit Setup
      7. 8.3.7  Battery Cell Configuration
      8. 8.3.8  Device HIZ State
      9. 8.3.9  USB On-The-Go (OTG)
      10. 8.3.10 Converter Operation
      11. 8.3.11 Inductance Detection Through IADPT Pin
      12. 8.3.12 Converter Compensation
      13. 8.3.13 Continuous Conduction Mode (CCM)
      14. 8.3.14 Pulse Frequency Modulation (PFM)
      15. 8.3.15 Switching Frequency and Dithering Feature
      16. 8.3.16 Current and Power Monitor
        1. 8.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)
      17. 8.3.17 Input Source Dynamic Power Management
      18. 8.3.18 Input Current Optimizer (ICO)
      19. 8.3.19 Two-Level Adapter Current Limit (Peak Power Mode)
      20. 8.3.20 Processor Hot Indication
        1. 8.3.20.1 PROCHOT During Low Power Mode
        2. 8.3.20.2 PROCHOT Status
      21. 8.3.21 Device Protection
        1. 8.3.21.1 Watchdog Timer
        2. 8.3.21.2 Input Overvoltage Protection (ACOV)
        3. 8.3.21.3 Input Overcurrent Protection (ACOC)
        4. 8.3.21.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.21.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.21.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 8.3.21.7 Battery Short Protection (BATSP)
        8. 8.3.21.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 8.3.21.9 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
      2. 8.4.2 USB On-The-Go
      3. 8.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
        1. 8.5.1.1 Timing Diagrams
        2. 8.5.1.2 Data Validity
        3. 8.5.1.3 START and STOP Conditions
        4. 8.5.1.4 Byte Format
        5. 8.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 8.5.1.6 Target Address and Data Direction Bit
        7. 8.5.1.7 Single Read and Write
        8. 8.5.1.8 Multi-Read and Multi-Write
        9. 8.5.1.9 Write 2-Byte I2C Commands
    6. 8.6 Register Map
      1. 8.6.1  ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
      2. 8.6.2  ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
        1. 8.6.2.1 Battery Pre-Charge Current Clamp
      3. 8.6.3  ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      4. 8.6.4  ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
      5. 8.6.5  ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
      6. 8.6.6  IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
      7. 8.6.7  ADCVBUS/PSYS Register (I2C address = 27/26h)
      8. 8.6.8  ADCIBAT Register (I2C address = 29/28h)
      9. 8.6.9  ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
      10. 8.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
      11. 8.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]
      12. 8.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
      13. 8.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
      14. 8.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
      15. 8.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
      16. 8.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      17. 8.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
      18. 8.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
      19. 8.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
      20. 8.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
      21. 8.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
      22. 8.6.22 VSYS_MIN Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
      23. 8.6.23 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]
      24. 8.6.24 ID Registers
        1. 8.6.24.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
        2. 8.6.24.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D5h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 9.2.2.2 ACP-ACN Input Filter
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Output Capacitor
        6. 9.2.2.6 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Example Reference Top View
      2. 11.2.2 Inner Layer Layout and Routing Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]

Figure 8-32 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
7 6 5 4 3 2 1 0
VSYS_UVP EN_Dither VSYS_UVP_NO_HICCUP PP_VBUS_VAP STAT_VBUS_VAP
R/W R/W R/W R/W R
7 6 5 4 3 2 1 0
IDCHG_DEG2 IDCHG_TH2 PP_IDCHG2 STAT_IDCHG2 STAT_PTM
R/W R/W R/W R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-40 ChargeOption4 Register (I2C address = 3Dh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-5 VSYS_UVP R/W 000b

VSYS Under Voltage Lock Out After UVP is triggered the charger enters hiccup mode, and then the charger is latched off if the restart fails 7 times in 90s The hiccup mode during the UVP can be disabled by setting 0x37[10]=1.
VSYS_UVP 1S~5s VSYS_UVP 1S~5s

000b

 2.4 V(Default)

100b

 5.6 V

001b

 3.2 V 101b 6.4 V

010b

 4.0 V

110b

 7.2 V

011b

 4.8 V

111b

 8.0 V
4-3 EN_DITHER R/W 00b

Frequency Dither configuration

00b: Disable Dithering<default at POR>

01b: Dither 1X (±2% Fs dithering range)

10b: Dither 2X (±4% Fs dithering range)

11b: Dither 3X (±6% Fs dithering range)
2 VSYS_UVP_NO_HICCUP R/W 0b

Disable VSYS_UVP Hiccup mode operation:

0b: Enable VSYS_UVP Hiccup mode <default at POR>

1b: Disable VSYS_UVP Hiccup mode
1 PP_VBUS_VAP R/W 0b

VBUS_VAP PROCHOT Profile

0b: disable <default at POR>

1b: enable
0 STAT_VBUS_VAP R 0b PROCHOT profile VBUS_VAP status bit. The status is latched until a read from host.

0b: Not triggered <default at POR>

1b: Triggered
Table 8-41 ChargeOption4 Register (I2C address = 3Ch) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7-6 IDCHG_DEG2 R/W 01b

Battery discharge current limit 2 deglitch time(minimum value)

00b: 100 μs

01b: 1.6 ms <default at POR>

10b: 6 ms

11b: 12 ms
5-3 IDCHG_TH2 R/W 001b

Battery discharge current limit2 based on percentage of IDCHG_TH1. Note IDCHG_TH2 setting higher than 32256 mA should lose accuracy de-rating between target value and 32256 mA. (Recommend not to set higher than 20 A for 1S OTG boost operation)

000b: 125% IDCHG_TH1

001b: 150% IDCHG_TH1 <default at POR>

010b: 175% IDCHG_TH1

011b: 200% IDCHG_TH1

100b: 250% IDCHG_TH1

101b: 300% IDCHG_TH1

110b: 350% IDCHG_TH1

111b: 400% IDCHG_TH1
2 PP_IDCHG2 R/W 0b

IDCHG2 PROCHOT Profile

0b: disable <default at POR>

1b: enable
1 STAT_IDCHG2 R 0b

The status is latched until a read from host.

0b: Not triggered <default at POR>

1b: Triggered
0 STAT_PTM R 0b

PTM operation status bit monitor

0b: Not in PTM Operation <default at POR>

1b: In PTM Operation