JAJSEG4C December   2013  – July 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Wireless Power Consortium (WPCまたはQi)電磁誘導給電システム
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 A Brief Description of the Wireless System
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Details of a Qi Wireless Power System and bq51003 Power Transfer Flow Diagrams
      2. 8.3.2  Dynamic Rectifier Control
      3. 8.3.3  Dynamic Efficiency Scaling
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Input Overvoltage
      6. 8.3.6  Adapter Enable Functionality and EN1/EN2 Control
      7. 8.3.7  End Power Transfer Packet (WPC Header 0x02)
      8. 8.3.8  Status Outputs
      9. 8.3.9  WPC Communication Scheme
      10. 8.3.10 Communication Modulator
      11. 8.3.11 Adaptive Communication Limit
      12. 8.3.12 Synchronous Rectification
      13. 8.3.13 Temperature Sense Resistor Network (TS)
      14. 8.3.14 3-State Driver Recommendations for the TS-CTRL Pin
      15. 8.3.15 Thermal Protection
      16. 8.3.16 WPC v1.2 Compliance – Foreign Object Detection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 bq51003 Wireless Power Receiver Used as a Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Using the bq51003 as a Wireless Power Supply
          2. 9.2.1.2.2 Series and Parallel Resonant Capacitor Selection
          3. 9.2.1.2.3 COMM, CLAMP, and BOOT Capacitors
          4. 9.2.1.2.4 Control Pins and CHG
          5. 9.2.1.2.5 Current Limit and FOD
          6. 9.2.1.2.6 RECT and OUT Capacitance
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual Power Path: Wireless Power and DC Input
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Typical Characteristics

bq51003 C006_SLUSBC8.pngFigure 1. Rectifier Efficiency
bq51003 C002_SLUSBC8.pngFigure 3. Light Load System Efficiency Improvement Due to Dynamic Efficiency Scaling Feature
bq51003 C004_SLUSBC8.pngFigure 5. VRECT vs ILOAD at RILIM = 524 Ω and 1048 Ω
bq51003 C007_SLUSBC8.pngFigure 7. Output Ripple vs ILOAD (COUT = 1 µF) Without Communication
bq51003 Fig12.pngFigure 9. 0.5-A Instantaneous Load Dump
bq51003 Fig14.pngFigure 11. 0.5-A Load Dump Full System Response
bq51003 TS_Fault_lvsat9.gifFigure 13. TS Fault
bq51003 BQ51013A_BQ24180_TRACK_ILIM_lusay6.gifFigure 15. Adaptive Communication Limit Event Where the Current Limit is IOUT + 50 mA (IOUT-DC > 300 mA)
bq51003 C001_SLUSBC8.pngFigure 2. System Efficiency from DC Input to DC Output
bq51003 C003_SLUSBC8.pngFigure 4. VRECT vs ILOAD at RILIM = 524 Ω
bq51003 C005_SLUSBC8.pngFigure 6. ILOAD Sweep (I-V Curve)
bq51003 fig_11.gifFigure 8. VOUT vs Temperature
bq51003 Fig13.pngFigure 10. 0.5-A Load Step Full System Response
bq51003 overvoltage_lvsat9.gifFigure 12. Rectifier Overvoltage Clamp (fop = 110 kHz)
bq51003 BQ51013A_BQ24180_TRACK_ILIM_400mA.gifFigure 14. Adaptive Communication Limit Event Where the 400-mA Current Limit is Enabled (IOUT-DC < 300 mA)
bq51003 COMM_PKT.gifFigure 16. Rx Communication Packet Structure