JAJSG05G November   2009  – November 2022 CDC3RL02

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low Additive Noise
      2. 8.3.2 Regulated 1.8-V Externally Available I/O Supply
      3. 8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Clock Squarer
      2. 9.1.2 Output Stage
      3. 9.1.3 LDO
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-31347D2E-956A-445E-AE68-592AE583177A-low.gifFigure 6-1 YFP Package8-Pin DSBGATop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
VBATT A1 I Input to internal LDO
CLK_OUT1 A2 O Clock output 1
VLDO B1 O 1.8 V I/O supply for CDC3RL02 and external TCXO
CLK_REQ1 B2 I Clock request 1 (from peripheral) for Clock output 1
MCLK_IN C1 I Master clock input
CLK_REQ2 C2 I Clock request 2 (from peripheral) for Clock output 2
GND D1 – Ground
CLK_OUT2 D2 O Clock output 2
Table 6-2 YFP Package Pin Assignments
1 2
A VBATT CLK_OUT1
B VLDO CLK_REQ1
C MCLK_LIN CLK_REQ2
D GND CLK_OUT2