JAJSG05G November   2009  – November 2022 CDC3RL02

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low Additive Noise
      2. 8.3.2 Regulated 1.8-V Externally Available I/O Supply
      3. 8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Clock Squarer
      2. 9.1.2 Output Stage
      3. 9.1.3 LDO
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.

  • Bypass capacitors should be used on power supplies and should be placed as close as possible to the VBATT pin
  • Short trace-lengths should be used to avoid excessive loading
  • For improved performance on the clock output lines, use a ground trace on the sides of the clock trace to minimize crosstalk and EMI