Figure 9-3 provides an example in which single DAC channel is used to compare both high and low thresholds. A dual comparator is used per DAC channel, as shown. A voltage divider formed by resistors RA and RB are used in order to bring the signal level within the DAC range. Another pair of resistors, R1 and R2, are used to settle the low threshold as a factor of the high threshold. This configuration allows the use of a single DAC channel to monitor both the high- and low-threshold levels. Use open-drain comparators to provide the following advantages.
In the circuit depicted in Figure 9-3, the output of the circuit remains high as long as the signal input remains within the high- and low-threshold levels. Upon violation of any one threshold, the output goes low. Equation 3 provides the derivation of the low threshold voltage from the high threshold set by the DAC.
To monitor a power supply of 5 V within ±10%, place the nominal value at the DAC midcode. The output range of the DACx3508 is 0 V to 5 V, thus the midcode voltage output is 2.5 V. Therefore, RA and RB are chosen so that the voltage to be compared is 2.5 V. For this example, RA equals RB; use 10-kΩ resistors for both. One channel of the DACx3508 must be programmed to VTHLD-HI (for example, 2.5 V + 5% = 2.625 V). This result corresponds to a 10-bit DAC code of (210 / 5 V) × 2.625 V = 537.6 (0x21Ah). To generate VTHLD-LO (for example, 2.5 V – 5% = 2.405 V) from 2.625 V, the values of R1 and R2 are calculated as 7.5 kΩ and 82 kΩ, respectively, using Equation 3.
The following pseudocode is provided to help get started with the programmable window comparator application at the desired DAC value.
//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA> //Power-up the device and channels WRITE DEVICE_CONFIG(0x01), 0x0000 //Program 2.625V on channel A WRITE DACA_DATA(0x08), 0x0868 //10-bit MSB aligned