SLASF08 December   2021 DAC43508 , DAC53508

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configurations and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI
    7. 7.7  Timing Requirements: Logic
    8. 7.8  Timing Diagrams
    9. 7.9  Typical Characteristics: Static Performance
    10. 7.10 Typical Characteristics: Dynamic Performance
    11. 7.11 Typical Characteristics: General
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Update and LDAC Functionality
        3. 8.3.1.3 CLR Functionality
        4. 8.3.1.4 Output Amplifier
      2. 8.3.2 Reference
      3. 8.3.3 Power-On Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
    6. 8.6 Register Map
      1. 8.6.1 DEVICE_CONFIG Register (address = 01h) [reset = 00FFh]
      2. 8.6.2 STATUS_TRIGGER Register (address = 02h) [reset = 0000h]
      3. 8.6.3 BRDCAST Register (address = 03h) [reset = 0000h]
      4. 8.6.4 DACn_DATA Register (address = 08h to 0Fh) [reset = 0000h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Programmable Window Comparator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

Figure 9-3 provides an example in which single DAC channel is used to compare both high and low thresholds. A dual comparator is used per DAC channel, as shown. A voltage divider formed by resistors RA and RB are used in order to bring the signal level within the DAC range. Another pair of resistors, R1 and R2, are used to settle the low threshold as a factor of the high threshold. This configuration allows the use of a single DAC channel to monitor both the high- and low-threshold levels. Use open-drain comparators to provide the following advantages.

  • Generate a logic output level appropriate for the monitoring processor
  • Allow shorting of the two outputs to generate a single trigger

In the circuit depicted in Figure 9-3, the output of the circuit remains high as long as the signal input remains within the high- and low-threshold levels. Upon violation of any one threshold, the output goes low. Equation 3 provides the derivation of the low threshold voltage from the high threshold set by the DAC.

Equation 3. V T H L D - L O = V D A C × R 2 R 1 + R 2

To monitor a power supply of 5 V within ±10%, place the nominal value at the DAC midcode. The output range of the DACx3508 is 0 V to 5 V, thus the midcode voltage output is 2.5 V. Therefore, RA and RB are chosen so that the voltage to be compared is 2.5 V. For this example, RA equals RB; use 10-kΩ resistors for both. One channel of the DACx3508 must be programmed to VTHLD-HI (for example, 2.5 V + 5% = 2.625 V). This result corresponds to a 10-bit DAC code of (210 / 5 V) × 2.625 V = 537.6 (0x21Ah). To generate VTHLD-LO (for example, 2.5 V – 5% = 2.405 V) from 2.625 V, the values of R1 and R2 are calculated as 7.5 kΩ and 82 kΩ, respectively, using Equation 3.

The following pseudocode is provided to help get started with the programmable window comparator application at the desired DAC value.

//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA>
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program 2.625V on channel A
WRITE DACA_DATA(0x08), 0x0868 //10-bit MSB aligned