JAJSLP4 December   2021 DAC43508 , DAC53508

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI
    7. 7.7  Timing Requirements: Logic
    8. 7.8  Timing Diagrams
    9. 7.9  Typical Characteristics: Static Performance
    10. 7.10 Typical Characteristics: Dynamic Performance
    11. 7.11 Typical Characteristics: General
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Update and LDAC Functionality
        3. 8.3.1.3 CLR Functionality
        4. 8.3.1.4 Output Amplifier
      2. 8.3.2 Reference
      3. 8.3.3 Power-On Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
    6. 8.6 Register Map
      1. 8.6.1 DEVICE_CONFIG Register (address = 01h) [reset = 00FFh]
      2. 8.6.2 STATUS_TRIGGER Register (address = 02h) [reset = 0000h]
      3. 8.6.3 BRDCAST Register (address = 03h) [reset = 0000h]
      4. 8.6.4 DACn_DATA Register (address = 08h to 0Fh) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Programmable Window Comparator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, VREFIN = 2.5 V for VDD ≥ 2.7 V, VREFIN = 1.8 V for VDD ≤ 2.7 V, RL= 5 kΩ to AGND, CL = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC53508 10 Bits
DAC43508 8
INL Integral nonlinearity(1) –1 1 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error Code 0d into DAC 6 12 mV
Zero-code-error temperature coefficient Code 0d into DAC ±5 µV/°C
Offset error(1) –0.5 0.25 0.5 %FSR
Offset-error temperature coefficient(1) ±0.0003 %FSR/°C
Gain error(1) –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(1) ±0.0004 %FSR/°C
Full-scale error(4) 2.7 V ≤ VDD ≤ 5.5 V –0.5 0.25 0.5 %FSR
1.8 V ≤ VDD ≤ 2.7 V –1 0.5 1
Full-scale-error temperature coefficient(4) ±0.0004 %FSR/°C
OUTPUT
VOUTX Output voltage 0 5.5 V
CL Capacitive load(2) RL = Infinite 1 nF
2
Load regulation DAC at midscale,
‒10 mA ≤ IOUT ≤ +10 mA, VDD = 5.5 V		 0.1 mV/mA
Short-circuit current(3) VDD = 1.8 V 10 mA
VDD = 2.7 V 25
VDD = 5.5 V 50
Output voltage headroom To VDD, DAC output unloaded 0.05 V
Output voltage headroom(2) To VDD, load current = 10 mA at VDD = 5.5 V, load current = 3 mA at VDD = 2.7 V, load current = 1 mA at VDD = 1.8 V,
DAC code at full-scale		 10 %FSR
ZO DC output impedance DAC at midscale 0.25 Ω
DAC at code 4d 0.25
DAC at code 1016d 0.26
DC PSRR Power supply rejection ratio (dc) DAC at midscale, VDD = 5 V ±10% 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 10 µs
SR Slew rate VDD = 5.5 V 0.6 V/µs
Power-on glitch magnitude 110 mV
Vn Output noise f = 0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V		 40 µVpp
Vn Output noise f = 0.1 Hz to 100 kHz, DAC at midscale, 
VDD = 5.5 V		 0.05 mVrms
Vn Output noise density f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 µV/√Hz
f = 10 kHz, DAC at midscale, VDD = 5.5 V 0.2
AC PSRR Power-supply rejection ratio (ac) 200-mV, 50-Hz or 60-Hz sine wave superimposed on power-supply voltage, DAC at midscale –71 dB
Channel-to-channel ac crosstalk Full-scale swing on adjacent channel 1.5 nV-s
Channel-to-channel dc crosstalk Full-scale swing on all channels, measured channel at zero-scale or
full-scale		 0.05 LSB
Code change glitch impulse ±1-LSB change around midscale (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1-LSB change around midscale (including feedthrough) 25 mV
VOLTAGE REFERENCE INPUT
Reference input impedance All channels powered on 12.5 kΩ
Reference input capacitance 50 pF
DIGITAL INPUTS
Digital feedthrough SCLK = 1 MHz, DAC output static at midscale 20 nV-s
Pin capacitance Per pin 10 pF
POWER
IDD Current flowing into VDD Normal mode, all DACs at full-scale,
SPI static		 3 5 mA
All DAC channels powered down 50 µA
(1) End point fit between codes: code 4d to code 1016d for 10 bit, code 1d to code 251d for 8 bit.
(2) Characterized by design. Not production tested.
(3) Full-scale output shorted per channel to AGND or zero-scale output shorted to VDD.
(4) Code 1023d into DAC, no headroom.