JAJSGU1B January 2019 – May 2022 DLP4500NIR
Table 11-1 lists the termination requirements for the DMD interface. These series resistors should be placed as close to the DLPC350 pins as possible while following all PCB guidelines.
|DMD_D(23:0), DMD_TRC, DMD_SCTRL, DMD_LOADB, DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_CLK, and DMD_SAC_BUS||External 5-Ω series termination at the transmitter|
|DMD_DCLK||External 5-Ω series termination at the transmitter|
|DMD_DRC_OE||External 0-Ω series termination. This signal must be externally pulled-up to VDD_DMD via a 30-kΩ to 51-kΩ resistor|
DMD_CLK and DMD_SAC_CLK clocks should be equal lengths, as shown in Figure 11-1.