JAJSGU1B データシート

JAJSGU1B January 2019 – May 2022 DLP4500NIR

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FQD|98
- MCLG010B

サーマルパッド・メカニカル・データ

発注情報

jajsgu1b_oa

7.7 Timing Requirements

Over operating free-air temperature range (unless otherwise noted). This data sheet provides timing at the device pin.

		MIN	NOM	MAX	UNIT
t_su(1)	Setup time: DATA before rising or falling edge of DCLK ⁽¹⁾	0.7			ns
	Setup time: TRC before rising or falling edge of DCLK ⁽¹⁾	0.7
	Setup time: SCTRL before rising or falling edge of DCLK ⁽¹⁾	0.7
t_su(2)	Setup time: LOADB low before rising edge of DCLK ⁽¹⁾	0.7			ns
t_su(3)	Setup time: SAC_BUS low before rising edge of SAC_CLK ⁽¹⁾	1			ns
t_su(4)	Setup time: DRC_BUS high before rising edge of SAC_CLK ⁽¹⁾	1			ns
t_su(5)	Setup time: DRC_STROBE high before rising edge of SAC_CLK ⁽¹⁾	2			ns
t_h(1)	Hold time: DATA after rising or falling edge of DCLK ⁽¹⁾	0.7			ns
	Hold time: TRC after rising or falling edge of DCLK ⁽¹⁾	0.7
	Hold time: SCTRL after rising or falling edge of DCLK ⁽¹⁾	0.7
t_h(2)	Hold time: LOADB low after falling edge of DCLK ⁽¹⁾	0.7			ns
t_h(3)	Hold time: SAC_BUS low after rising edge of SAC_CLK ⁽¹⁾	1			ns
t_h(4)	Hold time: DRC_BUS after rising edge of SAC_CLK ⁽¹⁾	1			ns
t_h(5)	Hold time: DRC_STROBE after rising edge of SAC_CLK ⁽¹⁾	2			ns
t_r	Rise time (20% to 80%): DCLK / SAC_CLK, VREF = 1.8 V			1.08	ns
t_r	Rise time (20% to 80%): DATA / TRC / SCTRL / LOADB, VREF = 1.8 V			1.08	ns
t_f	Fall time (20% to 80%): DCLK / SAC_CLK, VREF = 1.8 V			1.08	ns
t_f	Fall time (20% to 80%): DATA / TRC / SCTRL / LOADB			1.08	ns
t_c1	Clock cycle: DCLK	8.33	10	12.5	ns
t_c3	Clock cycle: SAC_CLK	12.5	13.33	14.3	ns
t_w1	Pulse width high or low: DCLK	3.33			ns
t_w2	Pulse width low: LOADB	4.73			ns
t_w3	Pulse width high or low: SAC_CLK	5			ns
t_w5	Pulse width high: DRC_STROBE	7			ns

(1) Setup and hold times shown are for fast input slew rates >1 V/ns. For slow slew rates >0.5 V/ns and <1 V/ns, the setup and hold times are longer. For every 0.1 V/ns decrease in slew rate from 1 V/ns, add 150 ps on setup and hold.

Figure 7-2 Timing Diagram