JAJSGI1 November   2018 DLP4710

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      DLPDLP4710 0.47 1080pチップセット
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions – Connector Pins
    2.     Pin Functions – Test Pads
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Software Requirements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Interface
      2. 8.3.2 Low-Speed Interface
      3. 8.3.3 High-Speed Interface
      4. 8.3.4 Timing
    4. 8.4 Device Functional Modes
    5. 8.5 Optical Interface and System Image Quality Considerations
      1. 8.5.1 Optical Interface and System Image Quality
        1. 8.5.1.1 Numerical Aperture and Stray Light Control
        2. 8.5.1.2 Pupil Match
        3. 8.5.1.3 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Power-Up Procedure
    2. 10.2 Power Supply Power-Down Procedure
    3. 10.3 Power Supply Sequencing Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
      2. 12.1.2 デバイスのマーキング
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The DLP4710 device is a 0.47 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 1920 columns by 1080 rows in a square grid pixel arrangement. The electrical interface is Sub Low Voltage Differential Signaling (SubLVDS) data.

DLP4710 device is part of the chipset comprising the DLP4710 DMD, DLPC3439 or DLPC3479 controller, and DLPA3000 or DLPA3005 PMIC/LED driver. To ensure reliable operation, the DLP4710 DMD must always be used with either the DLPC3439 or DLPC3479 controller and the DLPA3000 or DLPA3005 PMIC/LED drivers.