During the power-up sequence, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD.
During the power-up sequence, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. Refer to Table 9-1 for the power-up sequence, delay requirements.
During the power-up sequence, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET.
Power supply slew rates during the power-up sequence are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Section 9.3.
During the power-up sequence, LPSDR input pins must not be driven high until after VDD/VDDI have settled at operating voltages listed in Section 6.4.