DLPS206 May   2021 DLPC7540

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 FPD-Link LVDS Electrical Characteristics
    11. 6.11 USB Electrical Characteristics
    12. 6.12 System Oscillator Timing Requirements
    13. 6.13 Power Supply and Reset Timing Requirements
    14. 6.14 DMD HSSI Timing Requirements
    15. 6.15 DMD Low-Speed LVDS Timing Requirements
    16. 6.16 V-by-One Interface General Timing Requirements
    17. 6.17 FPD-Link Interface General Timing Requirements
    18. 6.18 Source Frame Timing Requirements
    19. 6.19 Synchronous Serial Port Interface Timing Requirements
    20. 6.20 Master and Slave I2C Interface Timing Requirements
    21. 6.21 Programmable Output Clock Timing Requirements
    22. 6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    23. 6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    24. 6.24 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 V-by-One interface
      5. 7.3.5 DMD (HSSI) Interface
      6. 7.3.6 Program Memory Flash Interface
      7. 7.3.7 GPIO Supported Functionality
      8. 7.3.8 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
        2. 7.4.2.2 Low Latency Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Management
    2. 9.2 Hot Plug Usage
    3. 9.3 Power Supplies for Unused Input Source Interfaces
    4. 9.4 Power Supplies
      1. 9.4.1 1.15-V Power Supplies
      2. 9.4.2 1.21V Power Supply
      3. 9.4.3 1.8-V Power Supplies
      4. 9.4.4 3.3-V Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Layout Guidelines
      2. 10.1.2  Power Supply Layout Guidelines
      3. 10.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 10.1.4  Layout Guideline for DLPC7540 Reference Clock
        1. 10.1.4.1 Recommended Crystal Oscillator Configuration
      5. 10.1.5  V-by-One Interface Layout Considerations
      6. 10.1.6  FPD-Link Interface Layout Considerations
      7. 10.1.7  USB Interface Layout Considerations
      8. 10.1.8  DMD Interface Layout Considerations
      9. 10.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Package Data
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
      1. 11.4.1 Video Timing Parameter Definitions
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 FPD-Link Interface

The DLPC7540 supports two FPD-Link 5 lane ports which can be configured for single port use (Port A or Port B), or for dual port use (Port A and Port B). The third FPD port (Port C) is reserved for parallel port use only. FPD ports A and B support a limited set of remapping options within each port, but there is no remapping between ports. When utilizing this feature, each unique lane pair can only be mapped to one unique destination lane pair, and Intra-lane remapping (i.e. swapping P with N) is not supported. In addition, the A and B ports can be swapped. Lane and port remapping (specified in flash) can help with board layout as needed. The typical lane mapping is shown in Figure 7-2. An example of an alternate lane mapping is shown in Figure 7-3. The specific intra port remapping options available are shown in Table 7-2.

GUID-7112D385-D33E-40E0-985B-FDB2944D650F-low.gifFigure 7-2 Example of Typical FPD-Link Port Lane Mapping
GUID-BADCFE38-4A0B-475E-A13D-ACDE529AF386-low.gifFigure 7-3 Example of Alternate FPD-Link Port Lane Mapping
Table 7-2 FPD-Link Intra Port Data Mapping Options
Mapping Options for Ports A & BInput Data PortInternal Final Data Path
0FPDx_DATAA_P/NFPD_x_PA
1FPDx_DATAB_P/NFPD_x_PA
2FPDx_DATAC_P/NFPD_x_PA
3FPDx_DATAD_P/NFPD_x_PA
4FPDx_DATAE_P/NFPD_x_PA
4FPDx_DATAA_P/NFPD_x_PB
0FPDx_DATAB_P/NFPD_x_PB
1FPDx_DATAC_P/NFPD_x_PB
2FPDx_DATAD_P/NFPD_x_PB
3FPDx_DATAE_P/NFPD_x_PB
3FPDx_DATAA_P/NFPD_x_PC
4FPDx_DATAB_P/NFPD_x_PC
0FPDx_DATAC_P/NFPD_x_PC
1FPDx_DATAD_P/NFPD_x_PC
2FPDx_DATAE_P/NFPD_x_PC
2FPDx_DATAA_P/NFPD_x_PD
3FPDx_DATAB_P/NFPD_x_PD
4FPDx_DATAC_P/NFPD_x_PD
0FPDx_DATAD_P/NFPD_x_PD
1FPDx_DATAE_P/NFPD_x_PD
1FPDx_DATAA_P/NFPD_x_PE
2FPDx_DATAB_P/NFPD_x_PE
3FPDx_DATAC_P/NFPD_x_PE
4FPDx_DATAD_P/NFPD_x_PE
0FPDx_DATAE_P/NFPD_x_PE

Independent from the remapping of the physical FPD interface, the DLPC7540 supports a number of data mappings onto the actual physical interface. There are three different 30-bit data mappings, and two different 24-bit data mappings supported. FPD sources must match at least one of these mappings These are shown in Table 7-3, Table 7-4, Table 7-5, Table 7-6, and Table 7-7.

Table 7-3 FPD-Link Data Mapping onto Physical Interface (30-bit Mode 0)
Bit Mapping - 30-bit Mode 0 (1)
(30-bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2YCbCr 4:2:0Mapper Output
PA-6G/Y[4]Y[4]Y00[4]A(4)
PA-5R/Cr[9]Cb/Cr[9]Cb/C00r[9]B(9)
PA-4R/Cr[8]Cb/Cr[8]Cb/Cr00[8]B(8)
PA-3R/Cr[7]Cb/Cr[7]Cb/Cr00[7]B(7)
PA-2R/Cr[6]Cb/Cr[6]Cb/Cr00[6]B(6)
PA-1R/Cr[5]Cb/Cr[5]Cb/Cr00[5]B(5)
PA-0R/Cr[4]Cb/Cr[4]Cb/Cr00[4]B(4)
PB-6B/Cb[5]UnusedY01[5]C(5)
PB-5B/Cb[4]UnusedY01[4]C(4)
PB-4G/Y[9]Y[9]Y00[9]A(9)
PB-3G/Y[8]Y[8]Y00[8]A(8)
PB-2G/Y[7]Y[7]Y00[7]A(7)
PB-1G/Y[6]Y[6]Y00[6]A(6)
PB-0G/Y[5]Y[5]Y00[5]A(5)
PC-6Data EnData EnData EnData En
PC-5VSYNCVSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNCHSYNC
PC-3B/Cb[9]UnusedY01[9]C(9)
PC-2B/Cb[8]UnusedY01[8]C(8)
PC-1B/Cb[7]UnusedY01[7]C(7)
PC-0B/Cb[6]UnusedY01[6]C(6)
PD-63D_L/R_Ref3D_L/R_Ref3D_L/R_Ref3D_Ref
PD-5B/Cb[3]UnusedY01[3]C(3)
PD-4B/Cb[2]UnusedY01[2]C(2)
PD-3G/Y[3]Y[3]Y00[3]A(3)
PD-2G/Y[2]Y[2]Y00[2]A(2)
PD-1R/Cr[3]Cb/Cr[3]Cb/Cr00[3]B(3)
PD-0R/Cr[2]Cb/Cr[2]Cb/Cr00[2]B(2)
PE-6FieldFieldFieldField
PE-5B/Cb[1]UnusedY01[1]C(1)
PE-4B/Cb[0]UnusedY01[0]C(0)
PE-3G/Y[1]Y[1]Y00[1]A(1)
PE-2G/Y[0]Y[0]Y00[0]A(0)
PE-1R/Cr[1]Cb/Cr[1]Cb/Cr00[1]B(1)
PE-0R/Cr[0]Cb/Cr[0]Cb/Cr00[0]B(0)
(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.
Table 7-4 FPD-Link Data Mapping onto Physical Interface (30-bit Mode 1)
Bit Mapping - 30-bit Mode 1 (1)
(30-bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2YCbCr 4:2:0Mapper Output
PA-6G/Y[2]Y[2]Y00[2]A(2)
PA-5R/Cr[7]Cb/Cr[7]Cb/C00r[7]B(7)
PA-4R/Cr[6]Cb/Cr[6]Cb/Cr00[6]B(6)
PA-3R/Cr(5]Cb/Cr[5]Cb/Cr00[5]B(5)
PA-2R/Cr[4]Cb/Cr[4]Cb/Cr00[4]B(4)
PA-1R/Cr[3]Cb/Cr[3]Cb/Cr00[3]B(3)
PA-0R/Cr[2]Cb/Cr[2]Cb/Cr00[2]B(2)
PB-6B/Cb[3]UnusedY01[3]C(3)
PB-5B/Cb[2]UnusedY01[2]C(2)
PB-4G/Y[7]Y[7]Y00[7]A(7)
PB-3G/Y[6]Y[6]Y00[6]A(6)
PB-2G/Y[5]Y[5]Y00[5]A(5)
PB-1G/Y[4]Y[4]Y00[4]A(4)
PB-0G/Y[3]Y[3]Y00[3]A(3)
PC-6Data EnData EnData EnData En
PC-5VSYNCVSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNCHSYNC
PC-3B/Cb[7]UnusedY01[7]C(7)
PC-2B/Cb[6]UnusedY01[6]C(6)
PC-1B/Cb[5]UnusedY01[5]C(5)
PC-0B/Cb[4]UnusedY01[4]C(4)
PD-63D_L/R_Ref3D_L/R_Ref3D_L/R_Ref3D_Ref
PD-5B/Cb[9]UnusedY01[9]C(9)
PD-4B/Cb[8]UnusedY01[8]C(8)
PD-3G/Y[9]Y[9]Y00[9]A(9)
PD-2G/Y[8]Y[8]Y00[8]A(8)
PD-1R/Cr[9]Cb/Cr[9]Cb/Cr00[9]B(9)
PD-0R/Cr[8]Cb/Cr[8]Cb/Cr00[8]B(8)
PE-6FieldFieldFieldField
PE-5B/Cb[1]UnusedY01[1]C(1)
PE-4B/Cb[0]UnusedY01[0]C(0)
PE-3G/Y[1]Y[1]Y00[1]A(1)
PE-2G/Y[0]Y[0]Y00[0]A(0)
PE-1R/Cr[1]Cb/Cr[1]Cb/Cr00[1]B(1)
PE-0R/Cr[0]Cb/Cr[0]Cb/Cr00[0]B(0)
(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.
Table 7-5 FPD-Link Data Mapping onto Physical Interface (30-bit Mode 2)
Bit Mapping - 30-bit Mode 2 (1)
(30-bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2YCbCr 4:2:0Mapper Output
PA-6G/Y[0]Y[0]Y00[0]A(0)
PA-5R/Cr[5]Cb/Cr[5]Cb/C00r[5]B(5)
PA-4R/Cr[4]Cb/Cr[4]Cb/Cr00[4]B(4)
PA-3R/Cr(3]Cb/Cr[3]Cb/Cr00[3]B(3)
PA-2R/Cr[2]Cb/Cr[2]Cb/Cr00[2]B(2)
PA-1R/Cr[1]Cb/Cr[1]Cb/Cr00[1]B(1)
PA-0R/Cr[0]Cb/Cr[0]Cb/Cr00[0]B(0)
PB-6B/Cb[1]UnusedY01[1]C(1)
PB-5B/Cb[0]UnusedY01[0]C(0)
PB-4G/Y[5]Y[5]Y00[5]A(5)
PB-3G/Y[4]Y[4]Y00[4]A(4)
PB-2G/Y[3]Y[3]Y00[3]A(3)
PB-1G/Y[2]Y[2]Y00[2]A(2)
PB-0G/Y[1]Y[1]Y00[1]A(1)
PC-6Data EnData EnData EnData En
PC-5VSYNCVSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNCHSYNC
PC-3B/Cb[5]UnusedY01[5]C(5)
PC-2B/Cb[4]UnusedY01[4]C(4)
PC-1B/Cb[3]UnusedY01[3]C(3)
PC-0B/Cb[2]UnusedY01[2]C(2)
PD-63D_L/R_Ref3D_L/R_Ref3D_L/R_Ref3D_Ref
PD-5B/Cb[7]UnusedY01[7]C(7)
PD-4B/Cb[6]UnusedY01[6]C(6)
PD-3G/Y[7]Y[7]Y00[7]A(7)
PD-2G/Y[6]Y[6]Y00[6]A(6)
PD-1R/Cr[7]Cb/Cr[7]Cb/Cr00[7]B(7)
PD-0R/Cr[6]Cb/Cr[6]Cb/Cr00[6]B(6)
PE-6FieldFieldFieldField
PE-5B/Cb[9]UnusedY01[9]C(9)
PE-4B/Cb[8]UnusedY01[8]C(8)
PE-3G/Y[9]Y[9]Y00[9]A(9)
PE-2G/Y[8]Y[8]Y00[8]A(8)
PE-1R/Cr[9]Cb/Cr[9]Cb/Cr00[9]B(9)
PE-0R/Cr[8]Cb/Cr[8]Cb/Cr00[8]B(8)
(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.
Table 7-6 FPD-Link Data Mapping onto Physical Interface (24-bit Mode 0) (1)
Bit Mapping - 24-bit Mode 0 (2)
(24-bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2YCbCr 4:2:0Mapper Output
PA-6G/Y[0]Y[0]Y00[0]A(2)
PA-5R/Cr[5]Cb/Cr[5]Cb/C00r[5]B(7)
PA-4R/Cr[4]Cb/Cr[4]Cb/Cr00[4]B(6)
PA-3R/Cr(3]Cb/Cr[3]Cb/Cr00[3]B(5)
PA-2R/Cr[2]Cb/Cr[2]Cb/Cr00[2]B(4)
PA-1R/Cr[1]Cb/Cr[1]Cb/Cr00[1]B(3)
PA-0R/Cr[0]Cb/Cr[0]Cb/Cr00[0]B(2)
PB-6B/Cb[1]UnusedY01[1]C(3)
PB-5B/Cb[0]UnusedY01[0]C(2)
PB-4G/Y[5]Y[5]Y00[5]A(7)
PB-3G/Y[4]Y[4]Y00[4]A(6)
PB-2G/Y[3]Y[3]Y00[3]A(5)
PB-1G/Y[2]Y[2]Y00[2]A(4)
PB-0G/Y[1]Y[1]Y00[1]A(3)
PC-6Data EnData EnData EnData En
PC-5VSYNCVSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNCHSYNC
PC-3B/Cb[5]UnusedY01[5]C(7)
PC-2B/Cb[4]UnusedY01[4]C(6)
PC-1B/Cb[3]UnusedY01[3]C(5)
PC-0B/Cb[2]UnusedY01[2]C(4)
PD-63D_L/R_Ref or Field3D_L/R_Ref or Field3D_L/R_Ref or Field3D_Ref or Field
PD-5B/Cb[7]UnusedY01[7]C(9)
PD-4B/Cb[6]UnusedY01[6]C(8)
PD-3G/Y[7]Y[7]Y00[7]A(9)
PD-2G/Y[6]Y[6]Y00[6]A(8)
PD-1R/Cr[7]Cb/Cr[7]Cb/Cr00[7]B(9)
PD-0R/Cr[6]Cb/Cr[6]Cb/Cr00[6]B(8)
PE-6UnusedUnusedUnusedUnused
PE-5UnusedUnusedUnusedUnused
PE-4UnusedUnusedUnusedUnused
PE-3UnusedUnusedUnusedUnused
PE-2UnusedUnusedUnusedUnused
PE-1UnusedUnusedUnusedUnused
PE-0UnusedUnusedUnusedUnused
(1) To support 24 bit data, the mapper shifts each 8-bit color up by 2 bits, and forces output bits A[1], A[0], B[1], B[0], C[1], and C[0] to value '0'.
(2) Input data bits are defined with bit[7] as the most significant bit, and bit[0] as the least significant bit.
Table 7-7 FPD-Link Data Mapping onto Physical Interface (24-bit Mode 1) (1)
Bit Mapping - 24-bit Mode 1 (2)
(24-bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2YCbCr 4:2:0Mapper Output
PA-6G/Y[2]Y[2]Y00{2}A(4)
PA-5R/Cr[7]Cb/Cr[7]Cb/C00r[7]B(9)
PA-4R/Cr[6]Cb/Cr[6]Cb/Cr00[6]B(8)
PA-3R/Cr(5]Cb/Cr[5]Cb/Cr00[5]B(7)
PA-2R/Cr[4]Cb/Cr[4]Cb/Cr00[4]B(6)
PA-1R/Cr[3]Cb/Cr[3]Cb/Cr00[3]B(5)
PA-0R/Cr[2]Cb/Cr[2]Cb/Cr00[2]B(4)
PB-6B/Cb[3]UnusedY01[3]C(5)
PB-5B/Cb[2]UnusedY01[2]C(4)
PB-4G/Y[7]Y[7]Y00[7]A(9)
PB-3G/Y[6]Y[6]Y00[6]A(8)
PB-2G/Y[5]Y[5]Y00[5]A(7)
PB-1G/Y[4]Y[4]Y00[4]A(6)
PB-0G/Y[3]Y[3]Y00[3]A(5)
PC-6Data EnData EnData EnData En
PC-5VSYNCVSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNCHSYNC
PC-3B/Cb[7]UnusedY01[7]C(9)
PC-2B/Cb[6]UnusedY01[6]C(8)
PC-1B/Cb[5]UnusedY01[5]C(7)
PC-0B/Cb[4]UnusedY01[4]C(6)
PD-63D_L/R_Ref or Field3D_L/R_Ref or Field3D_L/R_Ref or Field3D_Ref or Field
PD-5B/Cb[1]UnusedY01[1]C(3)
PD-4B/Cb[0]UnusedY01[0]C(2)
PD-3G/Y[1]Y[1]Y00[1]A(3)
PD-2G/Y[0]Y[0]Y00[0]A(2)
PD-1R/Cr[1]Cb/Cr[1]Cb/Cr00[1]B(3)
PD-0R/Cr[0]Cb/Cr[0]Cb/Cr00[0]B(2)
PE-6UnusedUnusedUnusedUnused
PE-5UnusedUnusedUnusedUnused
PE-4UnusedUnusedUnusedUnused
PE-3UnusedUnusedUnusedUnused
PE-2UnusedUnusedUnusedUnused
PE-1UnusedUnusedUnusedUnused
PE-0UnusedUnusedUnusedUnused
(1) To support 24 bit data, the mapper shifts each 8-bit color up by 2 bits, and forces output bits A[1], A[0], B[1], B[0], C[1], and C[0] to value '0'.
(2) Input data bits are defined with bit[7] as the most significant bit, and bit[0] as the least significant bit.