JAJSID0B December   2019  – March 2020 DP83826E , DP83826I

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 改訂履歴
  5. 概要 (続き)
  6. Mode Comparison Tables
  7. Pin Configuration and Functions (ENHANCED Mode)
    1.     Pin Functions (ENHANCED Mode)
  8. Pin Configuration and Functions (BASIC Mode)
    1.     Pin Functions (BASIC Mode)
  9. Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 ESD Ratings
    3. 9.3 Recommended Operating Conditions
    4. 9.4 Thermal Information
    5. 9.5 Electrical Characteristics
    6. 9.6 Timing Requirements
    7. 9.7 Timing Diagrams
    8. 9.8 Typical Characteristics
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 10.3.2  Auto-MDIX Resolution
      3. 10.3.3  Wake-on-LAN Packet Detection
        1. 10.3.3.1 Magic Packet Structure
        2. 10.3.3.2 Magic Packet Example
        3. 10.3.3.3 Wake-on-LAN Configuration and Status
      4. 10.3.4  Low Power Modes
        1. 10.3.4.1 Active Sleep
        2. 10.3.4.2 IEEE Power-Down
        3. 10.3.4.3 Deep Power Down State
      5. 10.3.5  RMII Repeater Mode
      6. 10.3.6  Clock Output
      7. 10.3.7  Media Independent Interface (MII)
      8. 10.3.8  Reduced Media Independent Interface (RMII)
      9. 10.3.9  Serial Management Interface
        1. 10.3.9.1 Extended Register Space Access
        2. 10.3.9.2 Write Address Operation
        3. 10.3.9.3 Read Address Operation
        4. 10.3.9.4 Write (No Post Increment) Operation
        5. 10.3.9.5 Read (No Post Increment) Operation
        6. 10.3.9.6 Example Write Operation (No Post Increment)
      10. 10.3.10 100BASE-TX
        1. 10.3.10.1 100BASE-TX Transmitter
          1. 10.3.10.1.1 Code-Group Encoding and Injection
          2. 10.3.10.1.2 Scrambler
          3. 10.3.10.1.3 NRZ to NRZI Encoder
          4. 10.3.10.1.4 Binary to MLT-3 Converter
        2. 10.3.10.2 100BASE-TX Receiver
      11. 10.3.11 10BASE-Te
        1. 10.3.11.1 Squelch
        2. 10.3.11.2 Normal Link Pulse Detection and Generation
        3. 10.3.11.3 Jabber
        4. 10.3.11.4 Active Link Polarity Detection and Correction
      12. 10.3.12 Loopback Modes
        1. 10.3.12.1 Near-end Loopback
        2. 10.3.12.2 MII Loopback
        3. 10.3.12.3 PCS Loopback
        4. 10.3.12.4 Digital Loopback
        5. 10.3.12.5 Analog Loopback
        6. 10.3.12.6 Far-End (Reverse) Loopback
      13. 10.3.13 BIST Configurations
      14. 10.3.14 Cable Diagnostics
        1. 10.3.14.1 Time Domain Reflectometry (TDR)
        2. 10.3.14.2 Fast Link-Drop Functionality
      15. 10.3.15 LED and GPIO Configuration
    4. 10.4 Programming
      1. 10.4.1 Hardware Bootstraps Configuration
        1. 10.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 10.4.1.1.1 Bootstraps for PHY Address
        2. 10.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 10.4.1.2.1 Bootstraps for PHY Address
    5. 10.5 Register Maps
      1. 10.5.1  BMCR Register (Address = 0x0) [reset = 0x3100]
        1. Table 23. BMCR Register Field Descriptions
      2. 10.5.2  BMSR Register (Address = 0x1) [reset = 0x7849]
        1. Table 24. BMSR Register Field Descriptions
      3. 10.5.3  PHYIDR1 Register (Address = 0x2) [reset = 0x2000]
        1. Table 25. PHYIDR1 Register Field Descriptions
      4. 10.5.4  PHYIDR2 Register (Address = 0x3) [reset = 0xA130]
        1. Table 26. PHYIDR2 Register Field Descriptions
      5. 10.5.5  ANAR Register (Address = 0x4) [reset = 0x1E1]
        1. Table 27. ANAR Register Field Descriptions
      6. 10.5.6  ALNPAR Register (Address = 0x5) [reset = 0x0]
        1. Table 28. ALNPAR Register Field Descriptions
      7. 10.5.7  ANER Register (Address = 0x6) [reset = 0x4]
        1. Table 29. ANER Register Field Descriptions
      8. 10.5.8  ANNPTR Register (Address = 0x7) [reset = 0x2001]
        1. Table 30. ANNPTR Register Field Descriptions
      9. 10.5.9  ANLNPTR Register (Address = 0x8) [reset = 0x0]
        1. Table 31. ANLNPTR Register Field Descriptions
      10. 10.5.10 CR1 Register (Address = 0x9) [reset = 0x0]
        1. Table 32. CR1 Register Field Descriptions
      11. 10.5.11 CR2 Register (Address = 0xA) [reset = 0x0]
        1. Table 33. CR2 Register Field Descriptions
      12. 10.5.12 CR3 Register (Address = 0xB) [reset = 0x0]
        1. Table 34. CR3 Register Field Descriptions
      13. 10.5.13 REGCR Register (Address = 0xD) [reset = 0x0]
        1. Table 35. REGCR Register Field Descriptions
      14. 10.5.14 ADDAR Register (Address = 0xE) [reset = 0x0]
        1. Table 36. ADDAR Register Field Descriptions
      15. 10.5.15 FLDS Register (Address = 0xF) [reset = 0x0]
        1. Table 37. FLDS Register Field Descriptions
      16. 10.5.16 PHYSTS Register (Address = 0x10) [reset = 0x6]
        1. Table 38. PHYSTS Register Field Descriptions
      17. 10.5.17 PHYSCR Register (Address = 0x11) [reset = 0x108]
        1. Table 39. PHYSCR Register Field Descriptions
      18. 10.5.18 MISR1 Register (Address = 0x12) [reset = 0x0]
        1. Table 40. MISR1 Register Field Descriptions
      19. 10.5.19 MISR2 Register (Address = 0x13) [reset = 0x0]
        1. Table 41. MISR2 Register Field Descriptions
      20. 10.5.20 FCSCR Register (Address = 0x14) [reset = 0x0]
        1. Table 42. FCSCR Register Field Descriptions
      21. 10.5.21 RECR Register (Address = 0x15) [reset = 0x0]
        1. Table 43. RECR Register Field Descriptions
      22. 10.5.22 BISCR Register (Address = 0x16) [reset = 0x100]
        1. Table 44. BISCR Register Field Descriptions
      23. 10.5.23 RCSR Register (Address = 0x17) [reset = 0x1]
        1. Table 45. RCSR Register Field Descriptions
      24. 10.5.24 LEDCR Register (Address = 0x18) [reset = 0x480]
        1. Table 46. LEDCR Register Field Descriptions
      25. 10.5.25 PHYCR Register (Address = 0x19) [reset = 0x8000]
        1. Table 47. PHYCR Register Field Descriptions
      26. 10.5.26 10BTSCR Register (Address = 0x1A) [reset = 0x0]
        1. Table 48. 10BTSCR Register Field Descriptions
      27. 10.5.27 BICSR1 Register (Address = 0x1B) [reset = 0x7D]
        1. Table 49. BICSR1 Register Field Descriptions
      28. 10.5.28 BICSR2 Register (Address = 0x1C) [reset = 0x5EE]
        1. Table 50. BICSR2 Register Field Descriptions
      29. 10.5.29 CDCR Register (Address = 0x1E) [reset = 0x0]
        1. Table 51. CDCR Register Field Descriptions
      30. 10.5.30 PHYRCR Register (Address = 0x1F) [reset = 0x0]
        1. Table 52. PHYRCR Register Field Descriptions
      31. 10.5.31 MLEDCR Register (Address = 0x25) [reset = 0x41]
        1. Table 53. MLEDCR Register Field Descriptions
      32. 10.5.32 COMPT Register (Address = 0x27) [reset = 0x0]
        1. Table 54. COMPT Register Field Descriptions
      33. 10.5.33 10M_CFG Register (Address = 0x2A) [reset = 0x4000]
        1. Table 55. 10M_CFG Register Field Descriptions
      34. 10.5.34 FLD_CFG1 Register (Address = 0x117) [reset = 0x0]
        1. Table 56. FLD_CFG1 Register Field Descriptions
      35. 10.5.35 FLD_CFG2 Register (Address = 0x131) [reset = 0x0]
        1. Table 57. FLD_CFG2 Register Field Descriptions
      36. 10.5.36 CDSCR Register (Address = 0x170) [reset = 0x410]
        1. Table 58. CDSCR Register Field Descriptions
      37. 10.5.37 CDSCR2 Register (Address = 0x171) [reset = 0x0]
        1. Table 59. CDSCR2 Register Field Descriptions
      38. 10.5.38 TDR_172 Register (Address = 0x172) [reset = 0x0]
        1. Table 60. TDR_172 Register Field Descriptions
      39. 10.5.39 CDSCR3 Register (Address = 0x173) [reset = 0xD04]
        1. Table 61. CDSCR3 Register Field Descriptions
      40. 10.5.40 TDR_174 Register (Address = 0x174) [reset = 0x0]
        1. Table 62. TDR_174 Register Field Descriptions
      41. 10.5.41 TDR_175 Register (Address = 0x175) [reset = 0x1004]
        1. Table 63. TDR_175 Register Field Descriptions
      42. 10.5.42 TDR_176 Register (Address = 0x176) [reset = 0x5]
        1. Table 64. TDR_176 Register Field Descriptions
      43. 10.5.43 CDSCR4 Register (Address = 0x177) [reset = 0x1E00]
        1. Table 65. CDSCR4 Register Field Descriptions
      44. 10.5.44 TDR_178 Register (Address = 0x178) [reset = 0x2]
        1. Table 66. TDR_178 Register Field Descriptions
      45. 10.5.45 CDLRR1 Register (Address = 0x180) [reset = 0x0]
        1. Table 67. CDLRR1 Register Field Descriptions
      46. 10.5.46 CDLRR2 Register (Address = 0x181) [reset = 0x0]
        1. Table 68. CDLRR2 Register Field Descriptions
      47. 10.5.47 CDLRR3 Register (Address = 0x182) [reset = 0x0]
        1. Table 69. CDLRR3 Register Field Descriptions
      48. 10.5.48 CDLRR4 Register (Address = 0x183) [reset = 0x0]
        1. Table 70. CDLRR4 Register Field Descriptions
      49. 10.5.49 CDLRR5 Register (Address = 0x184) [reset = 0x0]
        1. Table 71. CDLRR5 Register Field Descriptions
      50. 10.5.50 CDLAR1 Register (Address = 0x185) [reset = 0x0]
        1. Table 72. CDLAR1 Register Field Descriptions
      51. 10.5.51 CDLAR2 Register (Address = 0x186) [reset = 0x0]
        1. Table 73. CDLAR2 Register Field Descriptions
      52. 10.5.52 CDLAR3 Register (Address = 0x187) [reset = 0x0]
        1. Table 74. CDLAR3 Register Field Descriptions
      53. 10.5.53 CDLAR4 Register (Address = 0x188) [reset = 0x0]
        1. Table 75. CDLAR4 Register Field Descriptions
      54. 10.5.54 CDLAR5 Register (Address = 0x189) [reset = 0x0]
        1. Table 76. CDLAR5 Register Field Descriptions
      55. 10.5.55 CDLAR6 Register (Address = 0x18A) [reset = 0x0]
        1. Table 77. CDLAR6 Register Field Descriptions
      56. 10.5.56 IO_CFG1 Register (Address = 0x302) [reset = 0x0]
        1. Table 78. IO_CFG1 Register Field Descriptions
      57. 10.5.57 LED0_GPIO_CFG Register (Address = 0x303) [reset = 0x8]
        1. Table 79. LED0_GPIO_CFG Register Field Descriptions
      58. 10.5.58 LED1_GPIO_CFG Register (Address = 0x304) [reset = 0xD]
        1. Table 80. LED1_GPIO_CFG Register Field Descriptions
      59. 10.5.59 LED2_GPIO_CFG Register (Address = 0x305) [reset = 0x0]
        1. Table 81. LED2_GPIO_CFG Register Field Descriptions
      60. 10.5.60 LED3_GPIO_CFG Register (Address = 0x306) [reset = 0x0]
        1. Table 82. LED3_GPIO_CFG Register Field Descriptions
      61. 10.5.61 CLK_OUT_LED_STATUS Register (Address = 0x308) [reset = 0x0]
        1. Table 83. CLK_OUT_LED_STATUS Register Field Descriptions
      62. 10.5.62 VOD_CFG1 Register (Address = 0x30B) [reset = 0xC00]
        1. Table 84. VOD_CFG1 Register Field Descriptions
      63. 10.5.63 VOD_CFG2 Register (Address = 0x30C) [reset = 0x410]
        1. Table 85. VOD_CFG2 Register Field Descriptions
      64. 10.5.64 VOD_CFG3 Register (Address = 0x30E) [reset = 0x0]
        1. Table 86. VOD_CFG3 Register Field Descriptions
      65. 10.5.65 ANA_LD_PROG_SL Register (Address = 0x404) [reset = 0x0]
        1. Table 87. ANA_LD_PROG_SL Register Field Descriptions
      66. 10.5.66 ANA_RX10BT_CTRL Register (Address = 0x40D) [reset = 0x0]
        1. Table 88. ANA_RX10BT_CTRL Register Field Descriptions
      67. 10.5.67 GENCFG Register (Address = 0x456) [reset = 0x8]
        1. Table 89. GENCFG Register Field Descriptions
      68. 10.5.68 PIN_CFG1 Register (Address = 0x459) [reset = 0x0]
        1. Table 90. PIN_CFG1 Register Field Descriptions
      69. 10.5.69 PIN_CFG2 Register (Address = 0x45A) [reset = 0x0]
        1. Table 91. PIN_CFG2 Register Field Descriptions
      70. 10.5.70 LEDCFG Register (Address = 0x460) [reset = 0x650]
        1. Table 92. LEDCFG Register Field Descriptions
      71. 10.5.71 IOCTRL Register (Address = 0x461) [reset = 0x0]
        1. Table 93. IOCTRL Register Field Descriptions
      72. 10.5.72 SOR1 Register (Address = 0x467) [reset = 0x0]
        1. Table 94. SOR1 Register Field Descriptions
      73. 10.5.73 SOR2 Register (Address = 0x468) [reset = 0x87]
        1. Table 95. SOR2 Register Field Descriptions
      74. 10.5.74 LEDCFG2 Register (Address = 0x469) [reset = 0x40]
        1. Table 96. LEDCFG2 Register Field Descriptions
      75. 10.5.75 RXFCFG1 Register (Address = 0x4A0) [reset = 0x1081]
        1. Table 97. RXFCFG1 Register Field Descriptions
      76. 10.5.76 RXFS Register (Address = 0x4A1) [reset = 0x1000]
        1. Table 98. RXFS Register Field Descriptions
      77. 10.5.77 RXFPMD1 Register (Address = 0x4A2) [reset = 0x0]
        1. Table 99. RXFPMD1 Register Field Descriptions
      78. 10.5.78 RXFPMD2 Register (Address = 0x4A3) [reset = 0x0]
        1. Table 100. RXFPMD2 Register Field Descriptions
      79. 10.5.79 RXFPMD3 Register (Address = 0x4A4) [reset = 0x0]
        1. Table 101. RXFPMD3 Register Field Descriptions
      80. 10.5.80 RXFSOP1 Register (Address = 0x4A5) [reset = 0x0]
        1. Table 102. RXFSOP1 Register Field Descriptions
      81. 10.5.81 RXFSOP2 Register (Address = 0x4A6) [reset = 0x0]
        1. Table 103. RXFSOP2 Register Field Descriptions
      82. 10.5.82 RXFSOP3 Register (Address = 0x4A7) [reset = 0x0]
        1. Table 104. RXFSOP3 Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 11.2.2 Design Requirements
        1. 11.2.2.1 Clock Requirements
          1. 11.2.2.1.1 Oscillator
          2. 11.2.2.1.2 Crystal
      3. 11.2.3 Detailed Design Procedure
        1. 11.2.3.1 MII Layout Guidelines
        2. 11.2.3.2 RMII Layout Guidelines
        3. 11.2.3.3 MDI Layout Guidelines
      4. 11.2.4 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Signal Traces
      2. 13.1.2 Return Path
      3. 13.1.3 Transformer Layout
        1. 13.1.3.1 Transformer Recommendations
      4. 13.1.4 Metal Pour
      5. 13.1.5 PCB Layer Stacking
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 サポート・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Register Maps

Table 21 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 21 should be considered as reserved locations and the register contents should not be modified.

Table 21. Device Registers

Address Acronym Register Name Section
0x0 BMCR Go
0x1 BMSR Go
0x2 PHYIDR1 Go
0x3 PHYIDR2 Go
0x4 ANAR Go
0x5 ALNPAR Go
0x6 ANER Go
0x7 ANNPTR Go
0x8 ANLNPTR Go
0x9 CR1 Go
0xA CR2 Go
0xB CR3 Go
0xD REGCR Go
0xE ADDAR Go
0xF FLDS Go
0x10 PHYSTS Go
0x11 PHYSCR Go
0x12 MISR1 Go
0x13 MISR2 Go
0x14 FCSCR Go
0x15 RECR Go
0x16 BISCR Go
0x17 RCSR Go
0x18 LEDCR Go
0x19 PHYCR Go
0x1A 10BTSCR Go
0x1B BICSR1 Go
0x1C BICSR2 Go
0x1E CDCR Go
0x1F PHYRCR Go
0x25 MLEDCR Go
0x27 COMPT Go
0x2A 10M_CFG Go
0x117 FLD_CFG1 Go
0x131 FLD_CFG2 Go
0x170 CDSCR Go
0x171 CDSCR2 Go
0x172 TDR_172 Go
0x173 CDSCR3 Go
0x174 TDR_174 Go
0x175 TDR_175 Go
0x176 TDR_176 Go
0x177 CDSCR4 Go
0x178 TDR_178 Go
0x180 CDLRR1 Go
0x181 CDLRR2 Go
0x182 CDLRR3 Go
0x183 CDLRR4 Go
0x184 CDLRR5 Go
0x185 CDLAR1 Go
0x186 CDLAR2 Go
0x187 CDLAR3 Go
0x188 CDLAR4 Go
0x189 CDLAR5 Go
0x18A CDLAR6 Go
0x302 IO_CFG1 Go
0x303 LED0_GPIO_CFG Go
0x304 LED1_GPIO_CFG Go
0x305 LED2_GPIO_CFG Go
0x306 LED3_GPIO_CFG Go
0x308 CLK_OUT_LED_STATUS Go
0x30B VOD_CFG1 Go
0x30C VOD_CFG2 Go
0x30E VOD_CFG3 Go
0x404 ANA_LD_PROG_SL Go
0x40D ANA_RX10BT_CTRL Go
0x456 GENCFG Go
0x459 PIN_CFG1 Go
0x45A PIN_CFG2 Go
0x460 LEDCFG Go
0x461 IOCTRL Go
0x467 SOR1 Go
0x468 SOR2 Go
0x469 LEDCFG2 Go
0x4A0 RXFCFG1 Go
0x4A1 RXFS Go
0x4A2 RXFPMD1 Go
0x4A3 RXFPMD2 Go
0x4A4 RXFPMD3 Go
0x4A5 RXFSOP1 Go
0x4A6 RXFSOP2 Go
0x4A7 RXFSOP3 Go

Complex bit access types are encoded to fit into small table cells. Table 22 shows the codes that are used for access types in this section.

Table 22. Device Access Type Codes

Access Type Code Description
Read Type
H H Set or cleared by hardware
R R Read
RC R
C
Read
to Clear
RH R
H
Read
Set or cleared by hardware
Write Type
W W Write
W, STRAP W Write
W, W1S W Write
W0C W
0C
Write
0 to clear
W1S W
1S
Write
1 to set
Reset or Default Value
-n Value after reset or the default value