JAJSID0B December   2019  – March 2020 DP83826E , DP83826I

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 改訂履歴
  5. 概要 (続き)
  6. Mode Comparison Tables
  7. Pin Configuration and Functions (ENHANCED Mode)
    1.     Pin Functions (ENHANCED Mode)
  8. Pin Configuration and Functions (BASIC Mode)
    1.     Pin Functions (BASIC Mode)
  9. Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 ESD Ratings
    3. 9.3 Recommended Operating Conditions
    4. 9.4 Thermal Information
    5. 9.5 Electrical Characteristics
    6. 9.6 Timing Requirements
    7. 9.7 Timing Diagrams
    8. 9.8 Typical Characteristics
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 10.3.2  Auto-MDIX Resolution
      3. 10.3.3  Wake-on-LAN Packet Detection
        1. 10.3.3.1 Magic Packet Structure
        2. 10.3.3.2 Magic Packet Example
        3. 10.3.3.3 Wake-on-LAN Configuration and Status
      4. 10.3.4  Low Power Modes
        1. 10.3.4.1 Active Sleep
        2. 10.3.4.2 IEEE Power-Down
        3. 10.3.4.3 Deep Power Down State
      5. 10.3.5  RMII Repeater Mode
      6. 10.3.6  Clock Output
      7. 10.3.7  Media Independent Interface (MII)
      8. 10.3.8  Reduced Media Independent Interface (RMII)
      9. 10.3.9  Serial Management Interface
        1. 10.3.9.1 Extended Register Space Access
        2. 10.3.9.2 Write Address Operation
        3. 10.3.9.3 Read Address Operation
        4. 10.3.9.4 Write (No Post Increment) Operation
        5. 10.3.9.5 Read (No Post Increment) Operation
        6. 10.3.9.6 Example Write Operation (No Post Increment)
      10. 10.3.10 100BASE-TX
        1. 10.3.10.1 100BASE-TX Transmitter
          1. 10.3.10.1.1 Code-Group Encoding and Injection
          2. 10.3.10.1.2 Scrambler
          3. 10.3.10.1.3 NRZ to NRZI Encoder
          4. 10.3.10.1.4 Binary to MLT-3 Converter
        2. 10.3.10.2 100BASE-TX Receiver
      11. 10.3.11 10BASE-Te
        1. 10.3.11.1 Squelch
        2. 10.3.11.2 Normal Link Pulse Detection and Generation
        3. 10.3.11.3 Jabber
        4. 10.3.11.4 Active Link Polarity Detection and Correction
      12. 10.3.12 Loopback Modes
        1. 10.3.12.1 Near-end Loopback
        2. 10.3.12.2 MII Loopback
        3. 10.3.12.3 PCS Loopback
        4. 10.3.12.4 Digital Loopback
        5. 10.3.12.5 Analog Loopback
        6. 10.3.12.6 Far-End (Reverse) Loopback
      13. 10.3.13 BIST Configurations
      14. 10.3.14 Cable Diagnostics
        1. 10.3.14.1 Time Domain Reflectometry (TDR)
        2. 10.3.14.2 Fast Link-Drop Functionality
      15. 10.3.15 LED and GPIO Configuration
    4. 10.4 Programming
      1. 10.4.1 Hardware Bootstraps Configuration
        1. 10.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 10.4.1.1.1 Bootstraps for PHY Address
        2. 10.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 10.4.1.2.1 Bootstraps for PHY Address
    5. 10.5 Register Maps
      1. 10.5.1  BMCR Register (Address = 0x0) [reset = 0x3100]
        1. Table 23. BMCR Register Field Descriptions
      2. 10.5.2  BMSR Register (Address = 0x1) [reset = 0x7849]
        1. Table 24. BMSR Register Field Descriptions
      3. 10.5.3  PHYIDR1 Register (Address = 0x2) [reset = 0x2000]
        1. Table 25. PHYIDR1 Register Field Descriptions
      4. 10.5.4  PHYIDR2 Register (Address = 0x3) [reset = 0xA130]
        1. Table 26. PHYIDR2 Register Field Descriptions
      5. 10.5.5  ANAR Register (Address = 0x4) [reset = 0x1E1]
        1. Table 27. ANAR Register Field Descriptions
      6. 10.5.6  ALNPAR Register (Address = 0x5) [reset = 0x0]
        1. Table 28. ALNPAR Register Field Descriptions
      7. 10.5.7  ANER Register (Address = 0x6) [reset = 0x4]
        1. Table 29. ANER Register Field Descriptions
      8. 10.5.8  ANNPTR Register (Address = 0x7) [reset = 0x2001]
        1. Table 30. ANNPTR Register Field Descriptions
      9. 10.5.9  ANLNPTR Register (Address = 0x8) [reset = 0x0]
        1. Table 31. ANLNPTR Register Field Descriptions
      10. 10.5.10 CR1 Register (Address = 0x9) [reset = 0x0]
        1. Table 32. CR1 Register Field Descriptions
      11. 10.5.11 CR2 Register (Address = 0xA) [reset = 0x0]
        1. Table 33. CR2 Register Field Descriptions
      12. 10.5.12 CR3 Register (Address = 0xB) [reset = 0x0]
        1. Table 34. CR3 Register Field Descriptions
      13. 10.5.13 REGCR Register (Address = 0xD) [reset = 0x0]
        1. Table 35. REGCR Register Field Descriptions
      14. 10.5.14 ADDAR Register (Address = 0xE) [reset = 0x0]
        1. Table 36. ADDAR Register Field Descriptions
      15. 10.5.15 FLDS Register (Address = 0xF) [reset = 0x0]
        1. Table 37. FLDS Register Field Descriptions
      16. 10.5.16 PHYSTS Register (Address = 0x10) [reset = 0x6]
        1. Table 38. PHYSTS Register Field Descriptions
      17. 10.5.17 PHYSCR Register (Address = 0x11) [reset = 0x108]
        1. Table 39. PHYSCR Register Field Descriptions
      18. 10.5.18 MISR1 Register (Address = 0x12) [reset = 0x0]
        1. Table 40. MISR1 Register Field Descriptions
      19. 10.5.19 MISR2 Register (Address = 0x13) [reset = 0x0]
        1. Table 41. MISR2 Register Field Descriptions
      20. 10.5.20 FCSCR Register (Address = 0x14) [reset = 0x0]
        1. Table 42. FCSCR Register Field Descriptions
      21. 10.5.21 RECR Register (Address = 0x15) [reset = 0x0]
        1. Table 43. RECR Register Field Descriptions
      22. 10.5.22 BISCR Register (Address = 0x16) [reset = 0x100]
        1. Table 44. BISCR Register Field Descriptions
      23. 10.5.23 RCSR Register (Address = 0x17) [reset = 0x1]
        1. Table 45. RCSR Register Field Descriptions
      24. 10.5.24 LEDCR Register (Address = 0x18) [reset = 0x480]
        1. Table 46. LEDCR Register Field Descriptions
      25. 10.5.25 PHYCR Register (Address = 0x19) [reset = 0x8000]
        1. Table 47. PHYCR Register Field Descriptions
      26. 10.5.26 10BTSCR Register (Address = 0x1A) [reset = 0x0]
        1. Table 48. 10BTSCR Register Field Descriptions
      27. 10.5.27 BICSR1 Register (Address = 0x1B) [reset = 0x7D]
        1. Table 49. BICSR1 Register Field Descriptions
      28. 10.5.28 BICSR2 Register (Address = 0x1C) [reset = 0x5EE]
        1. Table 50. BICSR2 Register Field Descriptions
      29. 10.5.29 CDCR Register (Address = 0x1E) [reset = 0x0]
        1. Table 51. CDCR Register Field Descriptions
      30. 10.5.30 PHYRCR Register (Address = 0x1F) [reset = 0x0]
        1. Table 52. PHYRCR Register Field Descriptions
      31. 10.5.31 MLEDCR Register (Address = 0x25) [reset = 0x41]
        1. Table 53. MLEDCR Register Field Descriptions
      32. 10.5.32 COMPT Register (Address = 0x27) [reset = 0x0]
        1. Table 54. COMPT Register Field Descriptions
      33. 10.5.33 10M_CFG Register (Address = 0x2A) [reset = 0x4000]
        1. Table 55. 10M_CFG Register Field Descriptions
      34. 10.5.34 FLD_CFG1 Register (Address = 0x117) [reset = 0x0]
        1. Table 56. FLD_CFG1 Register Field Descriptions
      35. 10.5.35 FLD_CFG2 Register (Address = 0x131) [reset = 0x0]
        1. Table 57. FLD_CFG2 Register Field Descriptions
      36. 10.5.36 CDSCR Register (Address = 0x170) [reset = 0x410]
        1. Table 58. CDSCR Register Field Descriptions
      37. 10.5.37 CDSCR2 Register (Address = 0x171) [reset = 0x0]
        1. Table 59. CDSCR2 Register Field Descriptions
      38. 10.5.38 TDR_172 Register (Address = 0x172) [reset = 0x0]
        1. Table 60. TDR_172 Register Field Descriptions
      39. 10.5.39 CDSCR3 Register (Address = 0x173) [reset = 0xD04]
        1. Table 61. CDSCR3 Register Field Descriptions
      40. 10.5.40 TDR_174 Register (Address = 0x174) [reset = 0x0]
        1. Table 62. TDR_174 Register Field Descriptions
      41. 10.5.41 TDR_175 Register (Address = 0x175) [reset = 0x1004]
        1. Table 63. TDR_175 Register Field Descriptions
      42. 10.5.42 TDR_176 Register (Address = 0x176) [reset = 0x5]
        1. Table 64. TDR_176 Register Field Descriptions
      43. 10.5.43 CDSCR4 Register (Address = 0x177) [reset = 0x1E00]
        1. Table 65. CDSCR4 Register Field Descriptions
      44. 10.5.44 TDR_178 Register (Address = 0x178) [reset = 0x2]
        1. Table 66. TDR_178 Register Field Descriptions
      45. 10.5.45 CDLRR1 Register (Address = 0x180) [reset = 0x0]
        1. Table 67. CDLRR1 Register Field Descriptions
      46. 10.5.46 CDLRR2 Register (Address = 0x181) [reset = 0x0]
        1. Table 68. CDLRR2 Register Field Descriptions
      47. 10.5.47 CDLRR3 Register (Address = 0x182) [reset = 0x0]
        1. Table 69. CDLRR3 Register Field Descriptions
      48. 10.5.48 CDLRR4 Register (Address = 0x183) [reset = 0x0]
        1. Table 70. CDLRR4 Register Field Descriptions
      49. 10.5.49 CDLRR5 Register (Address = 0x184) [reset = 0x0]
        1. Table 71. CDLRR5 Register Field Descriptions
      50. 10.5.50 CDLAR1 Register (Address = 0x185) [reset = 0x0]
        1. Table 72. CDLAR1 Register Field Descriptions
      51. 10.5.51 CDLAR2 Register (Address = 0x186) [reset = 0x0]
        1. Table 73. CDLAR2 Register Field Descriptions
      52. 10.5.52 CDLAR3 Register (Address = 0x187) [reset = 0x0]
        1. Table 74. CDLAR3 Register Field Descriptions
      53. 10.5.53 CDLAR4 Register (Address = 0x188) [reset = 0x0]
        1. Table 75. CDLAR4 Register Field Descriptions
      54. 10.5.54 CDLAR5 Register (Address = 0x189) [reset = 0x0]
        1. Table 76. CDLAR5 Register Field Descriptions
      55. 10.5.55 CDLAR6 Register (Address = 0x18A) [reset = 0x0]
        1. Table 77. CDLAR6 Register Field Descriptions
      56. 10.5.56 IO_CFG1 Register (Address = 0x302) [reset = 0x0]
        1. Table 78. IO_CFG1 Register Field Descriptions
      57. 10.5.57 LED0_GPIO_CFG Register (Address = 0x303) [reset = 0x8]
        1. Table 79. LED0_GPIO_CFG Register Field Descriptions
      58. 10.5.58 LED1_GPIO_CFG Register (Address = 0x304) [reset = 0xD]
        1. Table 80. LED1_GPIO_CFG Register Field Descriptions
      59. 10.5.59 LED2_GPIO_CFG Register (Address = 0x305) [reset = 0x0]
        1. Table 81. LED2_GPIO_CFG Register Field Descriptions
      60. 10.5.60 LED3_GPIO_CFG Register (Address = 0x306) [reset = 0x0]
        1. Table 82. LED3_GPIO_CFG Register Field Descriptions
      61. 10.5.61 CLK_OUT_LED_STATUS Register (Address = 0x308) [reset = 0x0]
        1. Table 83. CLK_OUT_LED_STATUS Register Field Descriptions
      62. 10.5.62 VOD_CFG1 Register (Address = 0x30B) [reset = 0xC00]
        1. Table 84. VOD_CFG1 Register Field Descriptions
      63. 10.5.63 VOD_CFG2 Register (Address = 0x30C) [reset = 0x410]
        1. Table 85. VOD_CFG2 Register Field Descriptions
      64. 10.5.64 VOD_CFG3 Register (Address = 0x30E) [reset = 0x0]
        1. Table 86. VOD_CFG3 Register Field Descriptions
      65. 10.5.65 ANA_LD_PROG_SL Register (Address = 0x404) [reset = 0x0]
        1. Table 87. ANA_LD_PROG_SL Register Field Descriptions
      66. 10.5.66 ANA_RX10BT_CTRL Register (Address = 0x40D) [reset = 0x0]
        1. Table 88. ANA_RX10BT_CTRL Register Field Descriptions
      67. 10.5.67 GENCFG Register (Address = 0x456) [reset = 0x8]
        1. Table 89. GENCFG Register Field Descriptions
      68. 10.5.68 PIN_CFG1 Register (Address = 0x459) [reset = 0x0]
        1. Table 90. PIN_CFG1 Register Field Descriptions
      69. 10.5.69 PIN_CFG2 Register (Address = 0x45A) [reset = 0x0]
        1. Table 91. PIN_CFG2 Register Field Descriptions
      70. 10.5.70 LEDCFG Register (Address = 0x460) [reset = 0x650]
        1. Table 92. LEDCFG Register Field Descriptions
      71. 10.5.71 IOCTRL Register (Address = 0x461) [reset = 0x0]
        1. Table 93. IOCTRL Register Field Descriptions
      72. 10.5.72 SOR1 Register (Address = 0x467) [reset = 0x0]
        1. Table 94. SOR1 Register Field Descriptions
      73. 10.5.73 SOR2 Register (Address = 0x468) [reset = 0x87]
        1. Table 95. SOR2 Register Field Descriptions
      74. 10.5.74 LEDCFG2 Register (Address = 0x469) [reset = 0x40]
        1. Table 96. LEDCFG2 Register Field Descriptions
      75. 10.5.75 RXFCFG1 Register (Address = 0x4A0) [reset = 0x1081]
        1. Table 97. RXFCFG1 Register Field Descriptions
      76. 10.5.76 RXFS Register (Address = 0x4A1) [reset = 0x1000]
        1. Table 98. RXFS Register Field Descriptions
      77. 10.5.77 RXFPMD1 Register (Address = 0x4A2) [reset = 0x0]
        1. Table 99. RXFPMD1 Register Field Descriptions
      78. 10.5.78 RXFPMD2 Register (Address = 0x4A3) [reset = 0x0]
        1. Table 100. RXFPMD2 Register Field Descriptions
      79. 10.5.79 RXFPMD3 Register (Address = 0x4A4) [reset = 0x0]
        1. Table 101. RXFPMD3 Register Field Descriptions
      80. 10.5.80 RXFSOP1 Register (Address = 0x4A5) [reset = 0x0]
        1. Table 102. RXFSOP1 Register Field Descriptions
      81. 10.5.81 RXFSOP2 Register (Address = 0x4A6) [reset = 0x0]
        1. Table 103. RXFSOP2 Register Field Descriptions
      82. 10.5.82 RXFSOP3 Register (Address = 0x4A7) [reset = 0x0]
        1. Table 104. RXFSOP3 Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 11.2.2 Design Requirements
        1. 11.2.2.1 Clock Requirements
          1. 11.2.2.1.1 Oscillator
          2. 11.2.2.1.2 Crystal
      3. 11.2.3 Detailed Design Procedure
        1. 11.2.3.1 MII Layout Guidelines
        2. 11.2.3.2 RMII Layout Guidelines
        3. 11.2.3.3 MDI Layout Guidelines
      4. 11.2.4 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Signal Traces
      2. 13.1.2 Return Path
      3. 13.1.3 Transformer Layout
        1. 13.1.3.1 Transformer Recommendations
      4. 13.1.4 Metal Pour
      5. 13.1.5 PCB Layer Stacking
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 サポート・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions (ENHANCED Mode)

The ENHANCED mode is one of two modes that the DP83826 can be configured in at start-up. This mode allows the DP83826 to support real-time Ethernet applications in addition to the standard Ethernet applications. To configure the DP83826 to ENHANCED mode, leave ModeSelect (pin 1) unconnected or pull up with a resistor to VDDIO.

RHB Package
32-Pin QFN
(Top View)
DP83826E DP83826I pinout_rhb32_enhan_snls647.gif

Pin Functions (ENHANCED Mode)

PIN TYPE(1) DESCRIPTION
NAME NO
ModeSelect 1 Reset: I, PU Active: I, PU This pin selects the DP83826 operating mode: BASIC mode or ENHANCED mode. For ENHANCED mode, this pin shall be left NC or pulled-up with a resistor to VDDIO. For BASIC mode, this pin shall be shorted to GND.
CEXT 2 A External capacitor: Connect the CEXT pin through a 2-nF capacitor to GND.
VDDA3V3 3 Power Input analog supply: 3V3. For decoupling capacitor requirements, refer to Figure 30 section of data sheet.
RD_M 4 A Differential receive input (physical media dependent: PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode.
RD_P 5 A
TD_M 6 A Differential transmit output (PMD): These differential outputs are configured to either 10BASE-Te or 100BASE-TX signaling mode based on configuration chosen for PHY.
TD_P 7 A
XO 8 A Crystal output: Reference clock output. XO pin is used for crystal only. Leave this pin floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn 9 A Crystal or oscillator input clock:

MII mode, RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock.

RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock.

RBIAS 10 A RBIAS ( Bias resistor) value 6.49 kΩ with 1% precision connected to ground.
MDIO 11 Reset: I, PU Active: I/O, PU Management data I/O: Bi-directional management data signal that may be sourced by the management station or the PHY. This pin has internal pullup resistor of 10 kΩ. An external pullup resistor can be added if needed.
MDC 12 Reset: I, PD Active: I, PD Management data clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.
RX_D3 13 Reset: I, PD Active: O

Strap7

Receive data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII mode. 2-bits RX_D[1:0] is received in RMII mode.
RX_D2 14 Reset: I, PD Active: O

Strap8

RX_D1 15 Reset: I, PD Active: O

Strap9

RX_D0 16 Reset: I, PD Active: O

Strap0

VDDIO 17 Power I/O supply voltage: 3.3 V/1.8 V. For decoupling capacitor requirements, refer to Figure 30 section of data sheet.
RX_DV/ CRS_DV 18 Reset: I, PD Active: O

Strap10

Receive data valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode. In MII mode, this pin acts as RX_DV. In RMII mode, this pin acts as CRS_DV and combines the RMII Carrier and Receive Data Valid indications. This pin can be configured to RX_DV in RMII mode to enable RMII Repeater Mode.
RX_CLK/ 50MHz_RMII 19 Reset: I, PD Active: O MII receive clock: MII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data stream.

In RMII Master mode, this provides 50-MHz reference clock. In RMII Slave mode, this pin is not used and remains Input, pulldown.

RX_ER 20 Reset: I, PD Active: O

Strap6

Receive error: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode.

In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK.

In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. RX_ER is asserted high for every reception error, including errors during Idle.

PWRDN/INT 21 Reset: I, PU Active: I, PU Power down (default), interrupt: The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup resistor (9.5 kΩ). Some applications may require an external PU resistor.
TX_CLK 22 Reset: I, PD Active: O

Strap5

MII transmit clock: MII transmit clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has constant phase referenced to the input clock. Unused in RMII Mode.
TX_EN 23 Reset: I, PD Active: I, PD Transmit enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.
TX_D0 24 Reset: I, PD Active: I, PD Transmit data:

In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK.

In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock.

TX_D1 25 Reset: I, PD Active: I, PD
TX_D2 26 Reset: I, PD Active: I, PD
TX_D3 27 Reset: I, PD Active: I, PD
COL/LED2/ GPIO 28 Reset: I, PD Active: O

Strap4

Collision detect:

In MII mode: For Full-Duplex mode, this pin is always LOW. In Half Duplex mode, this pin is asserted HIGH only when both transmit and receive media are non-idle. This pin can be configured as a second additional LED driver (LED2) or general purpose I/O (GPIO) through register configurations.

In RMII mode, this pin acts as LED2 by default.

CRS/LED3 29 Reset: I, PD Active: O

Strap3

Carrier sense:

In MII mode this pin is asserted high when the receive or transmit medium is non-idle. Carrier sense and receive data valid. This pin can be configured as third LED (LED3) through register configuration.

In RMII mode, it is configured as LED3 by default.

LED0 30 Reset: I, PD Active: O

Strap2

LED0: This LED indicates transmit and receive activity in addition to the status of the Link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.
CLKOUT/ LED1 31 Reset: I, PD Active: O

Strap1

This pin provides 25-MHz reference clock from XI as default to clock. The output is not affected by Resets allowing Application to reset PHY without impacting other system getting impacted. The output clock switches off only by IEEE Power Down.

The pin can be configured to act as LED1 using strap or register configuration. The LED is ON when link is 100 M. LED remains OFF if Link is 10 M or no Link.

RST_N 32 Reset: I, PU Active: I, PU Reset low: RST_N pin is an active low reset input. Asserting this pin low for at least 25 μs forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.
I = Input, O = Output, I/O = Input/Ouput, A = Analog, PU or PD = Internal pullup or pulldown: Hardware bootstrap configuration