The BASIC mode is one of two modes that the DP83826 can be configured in at start-up. This mode allows the DP83826 to support all the standard Ethernet applications and matches a common pinout configuration used in many of today's applications. To configure the DP83826 to BASIC mode, ModeSelect (pin 1) should be shorted to GND.
|ModeSelect||1||Reset: I, PU Active: I, PU||This pin selects the operating mode: BASIC mode or ENHANCED mode. This pin shall be shorted to GND to configure DP83826 in BASIC mode. For ENHANCED mode, this pin shall be left NC or pulled-up with a resistor to VDDIO.|
|CEXT||2||A||External capacitor: Connect the CEXT pin through a 2-nF capacitor to GND.|
|VDDA3V3||3||Power||Input analog power supply pin: This pin shall be connected with 3.3 V. For decoupling capacitor requirements, refer to section of datasheet.|
|RD_M||4||A||Differential receive input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te or 100BASE-TX specific signaling mode.|
|TD_M||6||A||Differential transmit output (PMD): These differential outputs are configured to either 10BASE-Te or 100BASE-TX signaling mode based on the configuration chosen for the PHY.|
|XO||8||A||Crystal output: reference clock output. XO pin is used for crystal only. Leave this pin floating when a CMOS-level oscillator is connected to XI.|
|XI/50MHzIn||9||A||Crystal or oscillator input clock:
MII mode or RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock.
RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock.
|RBIAS||10||A||Bias resistance: RBIAS value 6.49 kΩ 1% precision connected to ground.|
|MDIO||11||Reset: I, PU Active: I/O, PU||Management data I/O: Bi-directional management data signal that may be sourced by the management station or the PHY. This pin has internal pullup resistor of 10 kΩ. An external pullup resistor can be added if needed.|
|MDC||12||Reset: I, PD Active: I, PD||Management data clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.|
|RX_D3||13||Reset: I, PD Active: O
|Receive data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII mode. 2-bits RX_D[1:0] is received in RMII mode.|
|RX_D2||14||Reset: I, PD Active: O
|RX_D1||15||Reset: I, PD Active: O
|RX_D0||16||Reset: I, PD Active: O
|VDDIO||17||Power||I/O supply voltage: 3.3 V or 1.8 V. For decoupling capacitor requirements, refer to section of datasheet.|
|RX_DV/ CRS_DV||18||Reset: I, PD Active: O
|Receive data valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode. In MII mode, this pin acts as RX_DV. In RMII mode, this pin acts as CRS_DV and combines the RMII carrier and receive data valid indications.|
|RX_CLK/ 50MHz_RMII||19||Reset: I, PD Active: O||MII receive clock: MII receive clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data stream.
In RMII master mode, this provides 50-MHz reference clock. In RMII slave mode, this pin is not used and remains Input/PD.
|RX_ER||20||Reset: I, PD Active: O
|Receive Error: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. RX_ER is asserted high for every reception error, including errors during Idle.|
|INT||21||Reset: I, PU; Active: I, PU||Interrupt: The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup resistor (9.5 kΩ). Some applications may require an external PU resistor.|
|TX_CLK||22||Reset: I, PD Active: O
|MII transmit clock: MII Transmit Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has constant phase referenced to the reference clock. Applications requiring such constant phase may use this feature. Unused in RMII Mode.|
|TX_EN||23||Reset: I, PD Active: I, PD||Transmit enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.|
|TX_D0||24||Reset: I, PD Active: I, PD||Transmit data:
In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK.
In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock.
|TX_D1||25||Reset: I, PD Active: I, PD|
|TX_D2||26||Reset: I, PD Active: I, PD|
|TX_D3||27||Reset: I, PD Active: I, PD|
|COL||28||Reset: I, PD Active: O
In MII mode: For Full-Duplex mode, this pin is always LOW. In Half Duplex mode, this pin is asserted HIGH only when both transmit and receive media are non-idle.
In RMII mode, this pin is not used.
|CRS||29||Reset: I, PD Active: O
In MII mode this pin is asserted high when the receive or transmit medium is non-idle.
carrier sense or receive data valid. In RMII mode, this pin is not used.
|LED0||30||Reset: I, PD Active: O
|LED0: This LED indicates transmit and receive activity in addition to the status of the Link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.|
|TX_ER/LED1||31||Reset: I, PD Active: O
|Transmit errors: The pin acts as TX_ER as default. This pin can be configured to LED1 thru register configuration. The LED is ON when link is 100 M. LED remains OFF if the Link is 10 M, or there is no Link.|
|RST_N||32||Reset: I, PU Active: I, PU||Reset low: RST_N pin is an active low reset input. Asserting this pin low for at least 25 μs forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.|