SNLS685 December   2020 DS160PR412

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x8 Lane Switching
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
      2. 8.2.2 DisplayPort Application
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

GUID-20201105-CA0I-1CNH-P72K-LRTT7HC1ZLBH-low.gif Figure 5-1 RUA Package42-Pin WQFNTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
MODE 41 I, 4-level Sets device control configuration modes. 4-level IO pin as defined in Table 7-3. The pin can be exercised at device power up or in normal operation mode.
L0: Pin Mode – device control configuration is done solely by strap pins.
L1 or L2: SMBus/I2C Slave Mode – device control configuration is done by an external controller with SMBus/I2C master. This pin along with ADDR pin sets devices slave address.
L3 (Float): RESERVED – TI internal test mode.
EQ0 /ADDR 40 I, 4-level In Pin Mode:
The EQ0 and EQ1 pins sets receiver linear equalization CTLE (AC gain) for all channels according to Table 7-1. These pins are sampled at device power-up only.
In SMBus/I2C Mode:
The ADDR pin in conjunction with MODE pin sets SMBus / I2C slave address according to Table 7-4. The pin is sampled at device power-up only.
EQ1 20 I, 4-level
GAIN /SDA 1 I, 4-level / IO In Pin Mode:
DC gain (broadbad gain including high frequency) from the input to the output of the device for all channels. Note the device also provides AC (high frequency) gain in the form of equalization controlled by EQ pins or SMBus/I2C registers.
In SMBus/I2C Mode:
3.3 V SMBus/I2C data. External pullup resistor such as 4.7 kΩ required for operation.
GND EP, 6, 9, 16, 21, 30, 39 P Ground reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return for the device. The EP should be connected to ground plane(s) through low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
RSVD 19 O TI internal test pin. Keep no connect.
PD 18 I, 3.3-V LVCMOS 2-level logic controlling the operating state of the redriver. Active in both Pin Mode and SMBus/I2C Mode. The pin is used part of PCIe RX_DET state machine as outlined in Table 7-2.
High: Power down for all channels
Low: Power up, normal operation for all channels
RX_DET /SCL 42 I, 4-level / IO In Pin Mode:
Sets receiver detect state machine options according to Table 7-2. The pin is sampled at device power-up only.
In SMBus/I2C Mode:
3.3 V SMBus/I2C clock. External pullup resistor such as 4.7 kΩ required for operation.
RX0N 4 I Inverting differential RX inputs. Channel 0.
RX0P 3 I Noninverting differential RX inputs. Channel 0.
RX1N 8 I Inverting differential RX inputs. Channel 1.
RX1P 7 I Noninverting differential RX inputs. Channel 0.
RX2N 11 I Inverting differential RX inputs. Channel 2.
RX2P 10 I Noninverting differential RX inputs. Channel 2.
RX3N 15 I Inverting differential RX inputs. Channel 3.
RX3P 14 I Noninverting differential RX inputs. Channel 3.
SEL 17 I, 3.3 V LVCMOS Selects the mux path. Active in both Pin Mode and SMBus/I2C Mode. Note the SEL pin must be exercised in system implementations for mux selection between Port A vs Port B. The pin is used part of PCIe RX_DET state machine as outlined in Table 7-2.
L: Port A selected.
H: Port B selected.
TXA0N 37 O Inverting differential TX output – Port A, Channel 0.
TXA0P 38 O Non-inverting differential TX output – Port A, Channel 0.
TXA1N 33 O Inverting differential TX output – Port A, Channel 1.
TXA1P 34 O Non-inverting differential TX output – Port A, Channel 1.
TXA2N 28 O Inverting differential TX output – Port A, Channel 2.
TXA2P 29 O Non-inverting differential TX output – Port A, Channel 2.
TXA3N 24 O Inverting differential TX output – Port A, Channel 3.
TXA3P 25 O Non-inverting differential TX output – Port A, Channel 3.
TXB0N 35 O Inverting differential TX output – Port B, Channel 0.
TXB0P 36 O Non-inverting differential TX output – Port B, Channel 0.
TXB1N 31 O Inverting differential TX output – Port B, Channel 1.
TXB1P 32 O Non-inverting differential TX output – Port B, Channel 1.
TXB2N 26 O Inverting differential TX output – Port B, Channel 2.
TXB2P 27 O Non-inverting differential TX output – Port B, Channel 2.
TXB3N 22 O Inverting differential TX output – Port B, Channel 3.
TXB3P 23 O Non-inverting differential TX output – Port B, Channel 3.
VCC 5, 13 P Power supply, VCC = 3.3 V ± 10%. The VCC pins on this device should be connected through a low-resistance path to the board VCC plane.
VREG1 2 P Internal regulator output. Must add decoupling capacitor of 0.22 µF near the pin. Do not route the pin beyond the decoupling capacitor. Do not connect to VREG2. Do not use as a power supply for any other component on the board.
VREG2 12 P Internal regulator output. Must add decoupling caps of 0.22 µF near the pin. Do not route the pin beyond the decoupling capacitor. Do not connect to VREG1. Do not use as a power supply for any other component on the board.