JAJSHH9H May   2008  – May 2019 DS90LV028AQ-Q1


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      機能図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Descriptions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Performance Curves
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. Power Decoupling Recommendations
        2. Termination
        3. Input Failsafe Biasing
        4. Probing LVDS Transmission Lines
        5. Cables and Connectors, General Comments
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Differential Traces
      2. 10.1.2 PC Board Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Application Information

General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual at www.ti.com.

LVDS drivers and receivers are intended to be primarily used in a simple point-to-point configuration as is shown in Figure 17. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be used, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90LV028AQ differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground). The device will operate for receiver input voltages up to VCC, but exceeding VCC will turn on the ESD protection circuitry which will clamp the bus voltages.