SNLS488 March   2016 DS90UB921-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  PCLK Timing Requirements
    9. 6.9  Recommended Timing for the Serial Control Bus
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signal Filter
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 Input SSC Tolerance (SSCT)
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Remote Auto Power-Down Mode
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (TRFB)
      12. 7.3.12 Frequency Mode Optimizations
      13. 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
      14. 7.3.14 Internal Pattern Generation
      15. 7.3.15 GPIO[3:0] and GPO_REG[7:4]
        1. 7.3.15.1 GPIO[3:0] Enable Sequence
        2. 7.3.15.2 GPO_REG[7:4] Enable Sequence
      16. 7.3.16 I2S Transmitting
      17. 7.3.17 Built In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration and Status
          1. 7.3.17.1.1 Sample BIST Sequence
        2. 7.3.17.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AVMUTE Operation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.