8.3.8.2 Back Channel Configuration
The D_GPIO[3:0] pins can be configured to have different sampling rates depending on the mode or back channel frequency. The mode is controlled by register 0x43 (Table 11). The back channel frequency can be controlled in several ways:
- Register 0x23[6] can set the divider that controls the back channel frequency based on the internal oscillator. 0x23[6] = 0 sets the divider to 4 and 0x23[6] = 1 sets the divider to 2. As long as BC_HS_CTL (0x23[4]) is set to 0, the back channel frequency is either 5 Mbps or 10 Mbps based on this bit.
- Register 0x23[4] can enable the high-speed back channel. This can also be pin-strapped through MODE_SEL1 (see Table 3). This bit overrides 0x23[6] and sets the divider for the back channel frequency to 1. Setting this bit to 1 sets the back channel frequency to 20 Mbps.
The back channel frequency has variation of ±20%.
NOTE
The back channel frequency must be set to 5 Mbps when paired with a DS90UB925Q-Q1, DS90UB925AQ-Q1, or DS90UB927Q-Q1. See Table 3 for details about configuring the D_GPIOs in various modes.
Table 3. Back Channel D_GPIO Effective Frequency
HSCC_MODE (0x43[2:0]) |
MODE |
NUMBER OF D_GPIOs |
SAMPLES PER FRAME |
D_GPIO EFFECTIVE FREQUENCY(1) (kHz) |
D_GPIOs ALLOWED |
5 Mbps BC(2) |
10 Mbps BC(3) |
20 Mbps BC(4) |
000 |
Normal |
4 |
1 |
33 |
66 |
133 |
D_GPIO[3:0] |
011 |
Fast |
4 |
6 |
200 |
400 |
800 |
D_GPIO[3:0] |
010 |
Fast |
2 |
10 |
333 |
666 |
1333 |
D_GPIO[1:0] |
001 |
Fast |
1 |
15 |
500 |
1000 |
2000 |
D_GPIO0 |
(1) The effective frequency assumes the worst-case back channel frequency (–20%) and a 4×sampling rate.
(2) 5 Mbps corresponds to BC FREQ SELECT = 0 & BC_HS_CTL = 0.
(3) 10 Mbps corresponds to BC FREQ SELECT = 1 & BC_HS_CTL = 0.
(4) 20 Mbps corresponds to BC FREQ SELECT = X & BC_HS_CTL = 1.