JAJSM26C September   2000  – January 2022 INA126 , INA2126

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: INA126
    5. 6.5 Thermal Information: INA2126
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single-Supply Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Gain
        2. 8.2.2.2 Offset Trimming
        3. 8.2.2.3 Input Bias Current Return
        4. 8.2.2.4 Input Common-Mode Range
        5. 8.2.2.5 Input Protection
        6. 8.2.2.6 Channel Crosstalk—Dual Version
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Low-Voltage Operation
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 PSpice® for TI
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Offset Trimming

The INAx126 family features low offset voltage and offset voltage drift. Most applications require no external offset adjustment. Figure 8-2 shows an optional circuit for trimming the output offset voltage. The voltage applied to the Ref pin is added to the output signal. An operational amplifier buffer provides low impedance at the Ref pin to preserve good common-mode rejection.

GUID-BEC5CEA7-89FD-446A-840D-1EBFCD5F4801-low.gifFigure 8-2 Optional Trimming of Output Offset Voltage