JAJSM26C September   2000  – January 2022 INA126 , INA2126

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: INA126
    5. 6.5 Thermal Information: INA2126
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single-Supply Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Gain
        2. 8.2.2.2 Offset Trimming
        3. 8.2.2.3 Input Bias Current Return
        4. 8.2.2.4 Input Common-Mode Range
        5. 8.2.2.5 Input Protection
        6. 8.2.2.6 Channel Crosstalk—Dual Version
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Low-Voltage Operation
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 PSpice® for TI
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20C4CCB9-ACCF-41E7-9B91-C4C6A71B527C-low.gif Figure 5-1 INA126: P (8-Pin PDIP), D (8-Pin SOIC), and DGK (8-Pin VSSOP) Packages, Top View
Table 5-1 Pin Functions: INA126
PIN I/O DESCRIPTION
NO. NAME
1, 8 RG — Gain setting pin. For gains greater than 5 place a gain resistor between pin 1 and pin 8.
2 V–IN I Negative input
3 V+IN I Positive input
4 V– — Negative supply
5 Ref I Reference input. This pin must be driven by a low impedance or connected to ground.
6 VO O Output
7 V+ — Positive supply
GUID-D926D5D7-3EEF-41A6-8CF2-D58F6E7F80AF-low.gif Figure 5-2 INA2126: N (16-Pin PDIP), D (16-Pin SOIC), and DBQ (16-Pin SSOP) Packages, Top View
Table 5-2 Pin Functions: INA2126
PIN I/O DESCRIPTION
NO. NAME
1 V–INA I Negative input for amplifier A
2 V+INA I Positive input for amplifier A
3, 4 RGA — Gain setting pin for amplifier A. For gains greater than 5 place a gain resistor between pin 3 and pin 4.
5 RefA I Reference input for amplifier A. This pin must be driven by a low impedance or connected to ground.
6 VOA O Output of amplifier A
7 SenseA I Feedback for amplifier A. Connect to VOA, amplifier A output.
8 V– — Negative supply
9 V+ — Positive supply
10 SenseB I Feedback for amplifier B. Connect to VOB, amplifier B output.
11 VOB O Output of amplifier B
12 RefB I Reference input for amplifier B. This pin must be driven by a low impedance or connected to ground.
13, 14 RGB — Gain setting pin for amplifier B. For gains greater than 5 place a gain resistor between pin 13 and pin 14.
15 V+INB I Positive input for amplifier B
16 V–INB I Negative input for amplifier B