JAJSN53A February   2012  – December 2021 INA230

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements (I2C)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Power Calculation
      3. 8.3.3 Alert Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
      2. 8.4.2 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Programming the Calibration Register
      2. 8.5.2 Programming the INA230 Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Default INA230 Settings
      5. 8.5.5 Bus Overview
        1. 8.5.5.1 Serial Bus Address
        2. 8.5.5.2 Serial Interface
      6. 8.5.6 Writing to and Reading From the I2C Serial Interface
        1. 8.5.6.1 High-Speed I2C Mode
      7. 8.5.7 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Register (00h, Read/Write)
      2. 8.6.2 AVG Bit Settings [11:9]
      3. 8.6.3 VBUS CT Bit Settings [8:6]
      4. 8.6.4 VSH CT Bit Settings [5:3]
      5. 8.6.5 Mode Settings [2:0]
      6. 8.6.6 Data Output Register
        1. 8.6.6.1 Shunt Voltage Register (01h, Read-Only)
        2. 8.6.6.2 Bus Voltage Register (02h, Read-Only) (1)
        3. 8.6.6.3 Power Register (03h, Read-Only)
        4. 8.6.6.4 Current Register (04h, Read-Only)
        5. 8.6.6.5 Calibration Register (05h, Read/Write)
        6. 8.6.6.6 Mask/Enable Register (06h, Read/Write)
        7. 8.6.6.7 Alert Limit Register (07h, Read/Write)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Side Sensing Circuit Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

at TA = 25°C, VS = 3.3 V, VSENSE = VIN+ - VIN- = 0 mV, VIN- = VBUS = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Shunt voltage input range –81.92 81.9175 mV
CMRR Common-mode rejection VCM = 0 V to 36 V, TA = –40°C to 125°C 120 140 dB
Vos Shunt offset voltage VCM = 12 V –9.8 ±25 µV
dVos/dT Shunt offset voltage drift TA = –40°C to +125°C ±0.05 ±0.1 µV/°C
PSRRSHUNT Power supply rejection ratio
(Current measurements)		 –3.0 µV/V
Vos_b Bus offset Voltage +2.3 ±15 mV
dVos_b/dT Bus offset voltage drift TA = –40°C to +125°C ±40 µV/°C
PSRRBUS Power supply rejection ratio
(Voltage measurements)		 0.4 mV/V
ZBUS BUS input impedance 830 kΩ
IB Input bias current IN+, IN-, Current measurement mode 10 µA
IB_SHDWN Input Leakage IN+, IN-, Shutdown Mode 0.1 0.5 µA
DC ACCURACY
ADC Resolution TA = –40°C to 125°C 16 Bits
1 LSB step size Shunt Voltage 2.5 µV
1 LSB step size Bus Voltage 1.25 mV
ADC Conversion-time
 		 CT bit = 000 140 154 µs
CT bit = 001 204 224 µs
CT bit = 010 332 365 µs
CT bit = 011 588 646 µs
CT bit = 100 1.100 1.21 ms
CT bit = 101 2.116 2.328 ms
CT bit = 110 4.156 4.572 ms
CT bit = 111 8.244 9.068 ms
GSERR Shunt voltage gain error ±0.010 ±0.3 %
GS_DRFT Shunt voltage gain error drift TA = –40°C to +125°C 10 50 ppm/°C
GBERR Bus voltage gain error ±0.010 ±0.3 %
GB_DRFT Bus voltage gain error drift TA = –40°C to +125°C 10 50 ppm/°C
DNL Differential Non-Linearity ±0.1 LSB
POWER SUPPLY
IQ Quiescent current VSENSE = 0 mV 330 420 µA
Shutdown 0.5 2 µA
SMBUS
SMBUS timeout 28 35 ms
DIGITAL INPUT / OUTPUT
Input capacitance 3 pF
VIH Logic input level, high 0.7 × VS 6 V
VIL Logic input level, low –0.5 0.3 × VS V
VHYS Hysteresis 500 mV
VOL Logic output level, low IOL = 3 mA 0 0.4 V
Digital leakage input current 0 ≤ VINPUT ≤ VS  0.1 1 µA