JAJSCP8B November   2016  – March 2017 ISO7710

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics—5-V Supply
    10. 6.10 Supply Current Characteristics—5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Switching Characteristics—5-V Supply
    16. 6.16 Switching Characteristics—3.3-V Supply
    17. 6.17 Switching Characteristics—2.5-V Supply
    18. 6.18 Insulation Characteristics Curves
    19. 6.19 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

Detailed Description

Overview

The ISO7710 device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The device also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 14, shows a functional block diagram of a typical channel.

Functional Block Diagram

ISO7710 fbd_sllsep3.gif Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 15 shows a conceptual detail of how the OOK scheme works.

ISO7710 on_off_keying_sllsem2.gif Figure 15. On-Off Keying (OOK) Based Modulation Scheme

Feature Description

The ISO7710 device is available in two default output state options to enable a variety of application uses. Table 1 lists the device features.

Table 1. Device Features

PART NUMBER MAXIMUM DATA RATE CHANNEL DIRECTION DEFAULT OUTPUT STATE PACKAGE RATED ISOLATION(1)
ISO7710 100 Mbps 1 Forward, 0 Reverse High DW-16 5000 VRMS / 8000 VPK
D-8 3000 VRMS / 4242 VPK
ISO7710F 100 Mbps 1 Forward, 0 Reverse Low DW-16 5000 VRMS / 8000 VPK
D-8 3000 VRMS / 4242 VPK
See the Safety-Related Certifications section for detailed isolation ratings.

Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO7710 device incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

Device Functional Modes

Table 2 lists the functional modes of ISO7710 device.

Table 2. Function Table(1)

VCC1 VCC2 INPUT
(IN)(3)
OUTPUT
(OUT)
COMMENTS
PU PU H H Normal Operation:
A channel output assumes the logic state of its input.
L L
Open Default Default mode: When IN is open, the corresponding channel output goes to its default logic state. Default is High for ISO7710 and Low for ISO7710F.
PD PU X Default Default mode: When VCC1 is unpowered, a channel output assumes the logic state based on the selected default option. Default is High for and Low for ISO7710F.
When VCC1 transitions from unpowered to powered-up, a channel output assumes the logic state of its input.
When VCC1 transitions from powered-up to unpowered, channel output assumes the selected default state.
X PD X Undetermined When VCC2 is unpowered, a channel output is undetermined (2).
When VCC2 transitions from unpowered to powered-up, a channel output assumes the logic state of its input
PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level
The outputs are in undetermined state when 1.7 V < VCC1, VCC2 < 2.25 V.
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.

Device I/O Schematics

ISO7710 device_IO_sllser9.gif Figure 16. Device I/O Schematics