JAJSJL2B December   2021  – December 2021 LDC3114-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Digital Interface
    7. 6.7 I2C Interface
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Multimode Operation
      2. 7.3.2 Multichannel and Single-Channel Operation
      3. 7.3.3 Raw Data Output
      4. 7.3.4 Button Output Interfaces
      5. 7.3.5 Programmable Button Sensitivity
      6. 7.3.6 Baseline Tracking
      7. 7.3.7 Integrated Button Algorithms
      8. 7.3.8 I2C Interface
        1. 7.3.8.1 I2C Interface Specifications
        2. 7.3.8.2 I2C Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Power Mode
      2. 7.4.2 Low Power Mode
      3. 7.4.3 Configuration Mode
    5. 7.5 Register Maps
      1. 7.5.1 LDC3114 Registers
      2. 7.5.2 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Theory of Operation
      2. 8.1.2  Designing Sensor Parameters
      3. 8.1.3  Setting COM Pin Capacitor
      4. 8.1.4  Defining Power-On Timing
      5. 8.1.5  Configuring Button or Raw Data Scan Rate
      6. 8.1.6  Programming Button or Raw Data Sampling Window
      7. 8.1.7  Scaling Frequency Counter Output
      8. 8.1.8  Setting Button Triggering Threshold
      9. 8.1.9  Tracking Baseline
      10. 8.1.10 Mitigating False Button Detections
        1. 8.1.10.1 Eliminating Common-Mode Change (Anti-Common)
        2. 8.1.10.2 Resolving Simultaneous Button Presses (Max-Win)
        3. 8.1.10.3 Overcoming Case Twisting (Anti-Twist)
        4. 8.1.10.4 Mitigating Metal Deformation (Anti-Deform)
      11. 8.1.11 Reporting Interrupts for Button Presses, Raw Data Ready and Error Conditions
      12. 8.1.12 Estimating Supply Current
    2. 8.2 Typical Application
      1. 8.2.1 Touch Button Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.8 I2C Interface

The LDC3114-Q1 features an I2C Interface that can be used to program the internal registers and read channel data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02 through 0x09) registers for button press data or raw channel data, RAW_DATAn_x (n = 0, 1, 2, or 3, for each channel, x= 1, 2, or 3 splitting 24-bit data over 3 8-bit register fields), the user should always read Register STATUS (Address 0x00) first to lock the data. The LDC3114-Q1 supports burst mode with auto-incrementing register addresses. The LDC3114-Q1 has a fixed I2C address of 0x2A.

For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The sequence of register writes is:

  • Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session.
  • Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1.
  • Perform I2C write to configure registers.
  • Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session.

After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. Figure 7-3 shows the waveform of the above process.

GUID-863A35C2-8570-4377-BDF6-D16EBAAD6797-low.gifFigure 7-3 Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for an I2C Write Handshake
Note: The I2C interface pin, the SDA, the SCL, and the INTB pins are all open-drain and 3.3-V compatible. These pins can be used to connect to an MCU which is supplied by 3.3-V supply without requiring voltage level translation between LDC3114-Q1 and the MCU.