SLAS990 Data sheet

SLAS990E January 2014 – October 2017 LM15851

PRODUCTION DATA.

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メカニカル・データ（パッケージ｜ピン）

NKE|68
- MPQS033A

サーマルパッド・メカニカル・データ

発注情報

6 Specifications

6.1 Absolute Maximum Ratings

The soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.⁽⁵⁾⁽¹⁾⁽³⁾

			MIN	MAX	UNIT
Supply voltage	1.2-V supply	VA12, VD12		1.4	V
	1.9-V supply	VA19		2.2	V
	1.2-V supply difference between VA12 and VD12		–200	200	mV
Voltage	On any input pin (except VIN+ or VIN–)		–0.15	V_(VA19) + 0.15	V
Voltage	On VIN+ or VIN–		0	2	V
Voltage difference	\|(VIN+) – (VIN–)\|⁽²⁾			2	V
	\|(DEVCLK+) – (DEVCLK–)\|			2
	\|(SYSREF+) – (SYSREF–)\|			2
	\|(~SYNC+) – (~SYNC–)\|			1
RF input power, P_I	On VIN+, VIN–, with proper input common mode maintained. F_IN ≥ 3 GHz, Z_(SOURCE) = 100 Ω, Input_Clamp_EN = 0 or 1			11.07	dBm
	On VIN+, VIN–, with proper input common mode maintained. F_IN = 1 GHz, Z_(SOURCE) = 100 Ω, Input_Clamp_EN = 1			14.95
	On VIN+, VIN–, with proper input common mode maintained. F_IN ≤ 100 MHz, Z_(SOURCE) = 100 Ω, Input_Clamp_EN = 1			20.97
Input current	At any pin other than VIN+ or VIN–⁽⁴⁾		–25	25	mA
	VIN+ or VIN–		–50	50	mA DC
	Package⁽⁴⁾ (sum of absolute value of all currents forced in or out, not including power supply current)			100	mA
Junction temperature, T_J	Power applied. Verified by High Temperature Operation Life testing to 1000 hours.		–40	150	°C
Storage temperature, T_stg			–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The analog inputs are protected as in the following circuit. Input-voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
LM15851 30180104.gif

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(4) When the input voltage at any pin (other than VIN+ or VIN–) exceeds the power supply limits (that is, less than GND or greater than VA19), the current at that pin must be limited to 25 mA. The 100-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies. This limit is not placed upon the power pins or thermal pad (GND).

(5) Reflow temperature profiles are different for lead-free and non-lead-free packages.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

All voltages are measured with respect to GND = 0 V, unless otherwise specified.

			MIN	MAX	UNIT
V_DD	Supply voltage	1.2-V supply: VA12, VD12	1.14	1.26	V
V_DD	Supply voltage	1.9-V supply: VA19	1.8	2	V
	Supply sequence (power-up and power-down)			1.9 supply ≥ 1.2 supply	V
V_CMI	Analog input common mode voltage		V_(VCMO) – 0.15	V_(VCMO) + 0.15	V
	VIN+, VIN– voltage (maintaining common mode)		0	V_(VA19)	V
	DEVCLK±, SYSREF±, ~SYNC± pin voltage range		0	V_(VA19)	V
V_ID(CLK)	Differential DEVCLK±, SYSREF±, ~SYNC± amplitude		0.4	2	V_PP
V_CM(CLK)	SYSREF±, ~SYNC± Common Mode		0.64	1.1	V
T_A	Ambient temperature		–40	85	°C
T_J	Junction temperature			135	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM15851	UNIT
		NKE (VQFN)
		68 PINS
R_θJA	Thermal resistance, junction-to-ambient	19.8	°C/W
R_θJCbot	Thermal resistance, junction-to-case (bottom)	2.7	°C/W
ψ_JB	Characterization parameter, junction-to-board	9.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for V_(VA12) = V_(VD12) = 1.2 V, V_(VA19) = 1.9 V, VIN full scale range at default setting (725 mV_PP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ_(DEVCLK) = 4 GHz at 0.5 V_PP with 50% duty cycle, R_(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at T_A = 25°C.⁽¹⁾⁽³⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
DYNAMIC PERFORMANCE CHARACTERISTICS
IMD₃	Third-order intermodulation distortion	F1 = 2110 MHz at −13 dBFS F2 = 2170 MHz at −13 dBFS			–64		dBc
DECIMATE-BY-4 MODE
SNR1	Signal-to-noise ratio, integrated across DDC alias protected output bandwidth Input frequency-dependent interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		59.9		dBFS
			T_A = T_MIN to T_MAX	56.2
			T_A = 25°C, calibration = BG		59.2
			T_A = T_MIN to T_MAX, calibration = BG	53.3
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode			56.4
SNR2	Signal-to-noise ratio, integrated across DDC alias protected output bandwidth Input frequency-dependent interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C⁽⁴⁾		60.1		dBFS
			T_A = T_MIN to T_MAX⁽⁴⁾	56.7
			T_A = 25°C, calibration = BG ⁽⁴⁾		60.2
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	56.7
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode⁽⁴⁾			57
SINAD1	Signal-to-noise and distortion ratio, integrated across DDC alias protected output bandwidth Input frequency-dependent interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		59.9		dBFS
			T_A = T_MIN to T_MAX	55.9
			T_A = 25°C, calibration = BG		59.2
			T_A = T_MIN to T_MAX, calibration = BG	53.1
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode			56.4
SINAD2	Signal-to-noise and distortion ratio, integrated across DDC alias protected output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C⁽⁴⁾		60.1		dBFS
			T_A = T_MIN to T_MAX⁽⁴⁾	56.3
			T_A = 25°C, calibration = BG ⁽⁴⁾		60.1
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	56.4
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode⁽⁴⁾			57
ENOB1	Effective number of bits, integrated across DDC alias protected output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, Decimate-by-4 mode	T_A = 25°C		9.7		Bits
			T_A = T_MIN to T_MAX	9.0
			T_A = 25°C, calibration = BG		9.5
			T_A = T_MIN to T_MAX, calibration = BG	8.5
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode			9.1
ENOB2	Effective number of bits, integrated across DDC alias protected output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C⁽⁴⁾		9.7		Bits
			T_A = T_MIN to T_MAX⁽⁴⁾	9.0
			T_A = 25°C, calibration = BG ⁽⁴⁾		9.7
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	9.1
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode⁽⁴⁾			8.5
SFDR1	Spurious-free dynamic range across entire Nyquist bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		70.1		dBFS
			T_A = T_MIN to T_MAX	59.2
			T_A = 25°C, calibration = BG		62.9
			T_A = T_MIN to T_MAX, calibration = BG	51.8
		F_IN = 2400 MHz, –1 dBFS, decimate-by-4 mode			66.4
SFDR2	Spurious-free dynamic range across entire Nyquist bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C⁽⁴⁾		71.6		dBFS
			T_A = T_MIN to T_MAX⁽⁴⁾	60
			T_A = 25°C, calibration = BG ⁽⁴⁾		74.8
			T_A = T_MIN to T_MAX, calibration = BG⁽⁴⁾	62.9
		F_IN = 2400 MHz, –1 dBFS, Decimate-by-4 mode⁽⁴⁾			80.4
ƒ_S/2	Interleaving offset spur at ½ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–72		dBFS
			T_A = T_MIN to T_MAX			–56
			T_A = 25°C, calibration = BG		–65
			T_A = T_MIN to T_MAX, calibration = BG			–50.5
ƒ_S/4	Interleaving offset spur at ¼ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–68		dBFS
			T_A = T_MIN to T_MAX			–55
			T_A = 25°C, calibration = BG		–62
			T_A = T_MIN to T_MAX, calibration = BG			–47.4
ƒ_S/2 – F_IN	Interleaving spur at ½ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–75		dBFS
			T_A = T_MIN to T_MAX			–62.3
			T_A = 25°C, calibration = BG		–70
			T_A = T_MIN to T_MAX, calibration = BG			–51.5
ƒ_S/4 + F_IN	Interleaving spur at ¼ sampling rate + input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–73		dBFS
			T_A = T_MIN to T_MAX			–58.9
			T_A = 25°C, calibration = BG		–65
			T_A = T_MIN to T_MAX, calibration = BG			–52.8
ƒ_S/4 – F_IN	Interleaving spur at ¼ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, Decimate-by-4 mode	T_A = 25°C		–78		dBFS
			T_A = T_MIN to T_MAX			–60.4
			T_A = 25°C, calibration = BG		–65
			T_A = T_MIN to T_MAX, calibration = BG			–52.3
THD	Total harmonic distortion⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–70		dBFS
			T_A = T_MIN to T_MAX			–59.5
			T_A = 25°C, calibration = BG		–73
			T_A = T_MIN to T_MAX, calibration = BG			–60
HD2	Second harmonic distortion⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–83		dBFS
			T_A = T_MIN to T_MAX			–62
			T_A = 25°C, calibration = BG		–78
			T_A = T_MIN to T_MAX, calibration = BG			–62.5
HD3	Third harmonic distortion⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-4 mode	T_A = 25°C		–72		dBFS
			T_A = T_MIN to T_MAX			–59.5
			T_A = 25°C, calibration = BG		–82
			T_A = T_MIN to T_MAX, calibration = BG			–62
DECIMATE-BY-8 MODE
SNR1	Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			63		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		61.6
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			54.6
SNR2	Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾			63.3		dBFS
SNR2		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾	Calibration = BG		63.3		dBFS
SINAD1	Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, Decimate-by-8 mode			63		dBFS
		F_IN = 600 MHz, –1 dBFS, Decimate-by-8 mode	Calibration = BG		61.6
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			54.6
SINAD2	Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾			63.3		dBFS
SINAD2		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁴⁾	Calibration = BG		63.3		dBFS
ENOB1	Effective number of bits, integrated across DDC output bandwidth Interleaving spurs included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			10.2		Bits
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		10.0
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			8.8
ENOB2	Effective number of bits, integrated across DDC output bandwidth Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾			10.2		Bits
ENOB2		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾	Calibration = BG		10.2		Bits
SFDR1	Spurious-free dynamic range Interleaving Spurs Included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			74.9		dBFS
SFDR1	Spurious-free dynamic range Interleaving Spurs Included	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		68.3		dBFS
SFDR2	Spurious-free dynamic range Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾			77.8		dBFS
SFDR2	Spurious-free dynamic range Interleaving spurs excluded	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode⁽⁵⁾	Calibration = BG		77.8		dBFS
ƒ_S/2	Interleaving offset spur at ½ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–73		dBFS
ƒ_S/2	Interleaving offset spur at ½ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–72		dBFS
ƒ_S/4	Interleaving offset spur at ¼ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–70		dBFS
ƒ_S/4	Interleaving offset spur at ¼ sampling rate⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–66		dBFS
ƒ_S/2 – F_IN	Interleaving spur at ½ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–76		dBFS
ƒ_S/2 – F_IN	Interleaving spur at ½ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–67		dBFS
ƒ_S/4 + F_IN	Interleaving spur at ¼ sampling rate + input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–72		dBFS
ƒ_S/4 + F_IN	Interleaving spur at ¼ sampling rate + input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–64		dBFS
ƒ_S/4 – F_IN	Interleaving spur at ¼ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–74		dBFS
ƒ_S/4 – F_IN	Interleaving spur at ¼ sampling rate – input frequency⁽⁵⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–67		dBFS
THD	Total harmonic distortion⁽⁶⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–70		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–72
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			–71
HD2	Second harmonic distortion⁽⁶⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–80		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–79
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			–78
HD3	Third harmonic distortion⁽⁶⁾	F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode			–74		dBFS
		F_IN = 600 MHz, –1 dBFS, decimate-by-8 mode	Calibration = BG		–80
		F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode			–-77
DDC CHARACTERISTICS
	Alias protection⁽²⁾			80			dB
	Alias protected bandwidth⁽²⁾			80			% of output BW
SFDR-DDC	Spurious-free dynamic range of digital down-converter⁽²⁾			100			dB
	Implementation loss⁽²⁾					0.5	dB
ANALOG INPUT CHARACTERISTICS
V_ID(VIN)	Full-scale analog-differential input range	Minimum FSR setting⁽⁶⁾			500		mV_PP
		Default FSR setting, T_A = T_MIN to T_MAX		650	725	800
		Maximum FSR setting⁽⁶⁾			950
C_I(VIN)	Analog input capacitance⁽²⁾	Differential			0.05		pF
C_I(VIN)	Analog input capacitance⁽²⁾	Each input pin to ground			1.5		pF
R_ID(VIN)	Differential input resistance			80	95	110	Ω
FPBW	Full power bandwidth	–3 dB — calibration = BG			2.8		GHz
FPBW	Full power bandwidth	–3 dB — calibration = FG			3.2		GHz
	Gain flatness	DC to 2 GHz			1.2		dB
		2 GHz to 4 GHz			3.8
		DC to 2 GHz — calibration = BG			1.5
		2 GHz to 4 GHz — calibration = BG			4.5
ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG)
V_(VCMO)	Common-mode output voltage	I_(VCMO) = ±100 µA, T_A = 25°C			1.225		V
V_(VCMO)	Common-mode output voltage	I_(VCMO) = ±100 µA, T_A = T_MIN to T_MAX		1.185		1.265	V
TCV_O(VCMO)	Common-mode output-voltage temperature coefficient	T_A = T_MIN to T_MAX			-21		ppm/°C
C_{(LOAD_VCMO)}	Maximum VCMO output load capacitance					80	pF
V_O(BG)	Bandgap reference output voltage	I_(BG) = ±100 µA, T_A = 25°C			1.248		V
V_O(BG)	Bandgap reference output voltage	I_(BG) = ±100 µA, T_A = T_MIN to T_MAX		1.195		1.3	V
TCV_ref(BG)	Bandgap reference voltage temperature coefficient	T_A = T_MIN to T_MAX, I_(BG) = ±100 µA			0		ppm/°C
C_{(LOAD_BG)}	Maximum bandgap reference output load capacitance					80	pF
TEMPERATURE DIODE CHARACTERISTICS
V_(TDIODE)	Temperature diode voltage slope	Offset voltage (approx. 0.77 V) varies with process and must be measured for each part. Offset measurement should be done with PowerDown=1 to minimize device self-heating.	100-µA forward current Device active		–1.6		mV/°C
V_(TDIODE)	Temperature diode voltage slope		100-µA forward current Device in power-down		–1.6		mV/°C
CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~)
V_ID(CLK)	Differential clock input level	Sine wave clock, T_A = T_MIN to T_MAX		0.4	0.6	2	V_PP
V_ID(CLK)	Differential clock input level	Square wave clock, T_A = T_MIN to T_MAX		0.4	0.6	2	V_PP
I_I(CLK)	Input current	V_I = 0 or V_I = V_A			±1		µA
C_I(CLK)	Input capacitance⁽²⁾	Differential			0.02		pF
C_I(CLK)	Input capacitance⁽²⁾	Each input to ground			1		pF
R_ID(CLK)	Differential input resistance	T_A = 25°C			95		Ω
R_ID(CLK)	Differential input resistance	T_A = T_MIN to T_MAX		80		110	Ω
CML OUTPUT CHARACTERISTICS (DS0–DS7±)
V_OD	Differential output voltage	Assumes ideal 100-Ω load Measured differentially Default pre-emphasis setting		280	305	330	mV peak
V_O(ofs)	Output offset voltage				0.6		V
I_OS	Output short-circuit current	Output+ and output– shorted together			±6		mA
I_OS	Output short-circuit current	Output+ or output– shorted to 0 V			12		mA
Z_OD	Differential output impedance				100		Ω
LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~)
V_IH	Logic high input voltage	See ⁽⁶⁾		0.83			V
V_IL	Logic low input voltage	See ⁽⁶⁾				0.4	V
C_I	Input capacitance⁽²⁾⁽⁷⁾	Each input to ground			1		pF
LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1)
V_OH	CMOS H level output	I_OH = –400 µA⁽⁶⁾		1.65	1.9		V
V_OL	CMOS L level output	I_OH = 400 µA⁽⁶⁾			0.01	0.15	V
POWER SUPPLY CHARACTERISTICS
I_(VA19)	Analog 1.9-V supply current	PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			560	607	mA
I_(VA12)	Analog 1.2-V supply current	PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			377	428	mA
I_(VD12)	Digital 1.2-V supply current	PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			541	826	mA
P_C	Power consumption	PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1			2.17	2.66	W
P_C	Power consumption	PD = 1			< 50		mW

(1) To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or more bypass capacitors.

(2) This parameter is specified by design and is not tested in production.

(3) Interleave related fixed frequency spurs at ƒ_S / 4 and ƒ_S / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The magnitude of these spurs is provided separately.

(4) Interleave related spurs at ƒ_S / 2 – F_IN, ƒ_S / 4 + F_IN and ƒ_S / 4 – F_IN are excluded from these performance calculations. The magnitude of these spurs is provided separately.

(5) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.

(6) This parameter is specified by design, characterization, or both and is not tested in production.

(7) The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately 0.4 pF.

6.6 Timing Requirements

			MIN	NOM	MAX	UNIT
DEVICE (SAMPLING) CLOCK
ƒ_(DEVCLK)	Input DEVCLK frequency	Sampling rate is equal to clock input	1		4	GHz
t_d(A)	Sampling (aperture) delay	Input CLK transition to sampling instant		0.64		ns
t_(AJ)	Aperture jitter			0.1		ps RMS
t_{(LAT_DDC)}	ADC core and DDC latency⁽²⁾	Decimation = 4, DDR = 1, P54 = 0		292		t_(DEVCLK)
		Decimation = 4, DDR = 1, P54 = 1		284
		Decimation = 8, DDR = 0, P54 = 0		384
		Decimation = 8, DDR = 0, P54 = 1		368
		Decimation = 8, DDR = 1, P54 = 0		392
		Decimation = 8, DDR = 1, P54 = 1		368
		Decimation = 10, DDR = 0, P54 = 0		386
		Decimation = 10, DDR = 1, P54 = 0		386
		Decimation = 16, DDR = 0, P54 = 0		608
		Decimation = 16, DDR = 0, P54 = 1		560
		Decimation = 16, DDR = 1, P54 = 0		608
		Decimation = 16, DDR = 1, P54 = 1		560
		Decimation = 20, DDR = 0, P54 = 0		568
		Decimation = 20, DDR = 1, P54 = 0		568
		Decimation = 32, DDR = 0, P54 = 0		1044
		Decimation = 32, DDR = 0, P54 = 1		948
		Decimation = 32, DDR = 1, P54 = 0		1044
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)
t_d(LMFC)	SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary⁽²⁾	All decimation modes		40		t_(DEVCLK)
t_d(TX)	LMFC to frame boundary delay - decimation modes Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data⁽³⁾	Decimation = 4, DDR = 1, P54 = 0		52.7		t_(DEVCLK)
		Decimation = 4, DDR = 1, P54 = 1		43.9
		Decimation = 8, DDR = 0, P54 = 0		60.7
		Decimation = 8, DDR = 0, P54 = 1		51.5
		Decimation = 8, DDR = 1, P54 = 0		52.7
		Decimation = 8, DDR = 1, P54 = 1		43.9
		Decimation = 10, DDR = 0, P54 = 0		60.7
		Decimation = 10, DDR = 1, P54 = 0		52.7
		Decimation = 16, DDR = 0, P54 = 0		60.7
		Decimation = 16, DDR = 0, P54 = 1		51.5
		Decimation = 16, DDR = 1, P54 = 0		52.7
		Decimation = 16, DDR = 1, P54 = 1		43.9
		Decimation = 20, DDR = 0, P54 = 0		60.7
		Decimation = 20, DDR = 1, P54 = 0		52.7
		Decimation = 32, DDR = 0, P54 = 0		60.7
		Decimation = 32, DDR = 0, P54 = 1		51.5
		Decimation = 32, DDR = 1, P54 = 0		52.7
t_su(SYNC~-F)	SYNC~ to LMFC setup time⁽¹⁾ Required SYNC~ setup time relative to the internal LMFC boundary.			40		t_(DEVCLK)
t_h(SYNC~-F)	SYNC~ to LMFC hold time⁽¹⁾ Required SYNC~ hold time relative to the internal LMFC boundary.			–8		t_(DEVCLK)
t_(SYNC~)	SYNC~ assertion time Required SYNC~ assertion time before deassertion to initiate a link resynchronization.			4		Frame clock cycles
t_d(LMFC)	Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary			40		t_(DEVCLK)
t_(ILA)	Duration of initial lane alignment sequence			4		Multi-frame clock cycles
SYSREF
t_su(SYS)	Setup time SYSREF relative to DEVCLK rising edge⁽⁶⁾			40		ps
t_h(SYS)	Hold time SYSREF relative to DEVCLK rising edge⁽⁶⁾			40		ps
t_{(PH_SYS)}	SYSREF assertion duration after rising edge event.		8			t_(DEVCLK)
t_{(PL_SYS)}	SYSREF deassertion duration after falling edge event.		8			t_(DEVCLK)
t_(SYS)	Period SYSREF±	DDR = 0, P54 = 0		K × F × 10		t_(DEVCLK)
		DDR = 0, P54 = 1		K × F × 8
		DDR = 1, P54 = 0		K × F × 5
		DDR = 1, P54 = 1		K × F × 4
SERIAL INTERFACE (REFER TO Figure 2)
ƒ_(SCK)	Serial clock frequency⁽²⁾				20	MHz
t_(PH)	Serial clock high time		20			ns
t_(PL)	Serial clock low time		20			ns
t_su	Serial-data to serial-clock rising setup time⁽²⁾		10			ns
t_h	Serial-data to serial clock rising hold time⁽²⁾		10			ns
t_(CSS)	SCS-to-serial clock rising setup time		10			ns
t_(CSH)	SCS-to-serial clock falling hold time		10			ns
t_(IAG)	Inter-access gap		10			ns

(1) This parameter must be met to achieve deterministic alignment of the data frame and NCO phase to other similar devices. If this parameter is not met the device will still function correctly but will not be aligned to other devices.

(2) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).

(3) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.

6.7 Internal Characteristics

PARAMETER		TEST CONDITIONS	NOM	MAX	UNIT
DEVICE (SAMPLING) CLOCK
t_d(A)	Sampling (aperture) delay	Input CLK transition to sampling instant	0.64		ns
t_(AJ)	Aperture jitter		0.1		ps RMS
CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION)
t_(CAL)	Calibration cycle time	Calibration = FG, T_AUTO=1		227 × 10⁶	t_(DEVCLK)
t_(CAL)	Calibration cycle time	Calibration = FG, T_AUTO=0		102 × 10⁶	t_(DEVCLK)
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)
t_d(LMFC)	SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary⁽²⁾	All decimation modes	40		t_(DEVCLK)
t_d(TX)	LMFC to frame boundary delay - decimation modes Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data⁽³⁾	Decimation = 4, DDR = 1, P54 = 0	52.7		t_(DEVCLK)
		Decimation = 4, DDR = 1, P54 = 1	43.9
		Decimation = 8, DDR = 0, P54 = 0	60.7
		Decimation = 8, DDR = 0, P54 = 1	51.5
		Decimation = 8, DDR = 1, P54 = 0	52.7
		Decimation = 8, DDR = 1, P54 = 1	43.9
		Decimation = 10, DDR = 0, P54 = 0	60.7
		Decimation = 10, DDR = 1, P54 = 0	52.7
		Decimation = 16, DDR = 0, P54 = 0	60.7
		Decimation = 16, DDR = 0, P54 = 1	51.5
		Decimation = 16, DDR = 1, P54 = 0	52.7
		Decimation = 16, DDR = 1, P54 = 1	43.9
		Decimation = 20, DDR = 0, P54 = 0	60.7
		Decimation = 20, DDR = 1, P54 = 0	52.7
		Decimation = 32, DDR = 0, P54 = 0	60.7
		Decimation = 32, DDR = 0, P54 = 1	51.5
		Decimation = 32, DDR = 1, P54 = 0	52.7
t_d(LMFC)	Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary		40		t_(DEVCLK)
t_(ILA)	Duration of initial lane alignment sequence		4		Multi-frame clock cycles

6.8 Switching Characteristics

Unless otherwise noted, these specifications apply for V_(VA12) = V_(VD12) = 1.2 V, V_(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ_(DEVCLK) = 4 GHz at 0.5 V_PP with 50% duty cycle, R_(RBIAS) = 3.3 kΩ ±0.1%, after a foreground mode calibration with timing calibration enabled. Typical values are at T_A = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL DATA OUTPUTS
	Serialized output bit rate		1		10	Gbps
	Serialized output bit rate	DDR = 0, P54 = 0		ƒ_S
		DDR = 0, P54 = 1		1.25 × ƒ_S
		DDR = 1, P54 = 0		2 × ƒ_S
		DDR = 1, P54 = 1		2.5 × ƒ_S
t_TLH	LH transition time — differential	10% to 90%, 8 Gbps		35		ps
t_THL	HL transition time — differential	10% to 90%, 8 Gbps		35		ps
UI	Unit interval	8 Gbps serial rate		125		ps
DDJ	Data dependent jitter	8 Gbps serial rate		11.3		ps
RJ	Random Jitter	8 Gbps serial rate		1.4		ps
SERIAL INTERFACE
t_(OZD)	SDO tri-state to driven	See Figure 2			5	ns
t_(ODZ)	SDO driven to tri-state		2.5		5	ns
t_(OD)	SDO output delay				20	ns

LM15851 JESD204_Synchronization_Timing.gif

Figure 1. JESD204 Synchronization

Figure 2. Serial Interface Timing

6.9 Typical Characteristics

Unless otherwise noted, these specifications apply for V_(VA12) = V_(VD12) = 1.2 V, V_(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ_(DEVCLK) = 4 GHz at 0.5 V_PP with 50% duty cycle, R_(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. T_A = 25°C. V_I = –1 dBFS.