SNVS430I May   2006  – March 2015 LM26001 , LM26001-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - LM26001
    3. 6.3 ESD Ratings - LM26001-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 FPWM
      3. 7.3.3 Enable
      4. 7.3.4 Soft-Start
      5. 7.3.5 Current Limit
      6. 7.3.6 Frequency Adjustment and Synchronization
      7. 7.3.7 VBIAS
      8. 7.3.8 Low VIN Operation and UVLO
      9. 7.3.9 PGOOD
    4. 7.4 Device Functional Modes
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting Output Voltage
        2. 8.2.2.2 Inductor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Bootstrap
        6. 8.2.2.6 Catch Diode
        7. 8.2.2.7 Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations and TSD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ

10 Layout

10.1 Layout Guidelines

Good board layout is critical for switching regulators such as the LM26001. First, the ground plane area must be sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the effects of switching noise.

Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise.

The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can cause duty cycle jitter which leads to increased spectral noise. Although the LM26001 has 100ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the important guidelines below will help minimize switching noise and its effect on current sensing.

The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors should be grounded to a large ground plane, with the bulk input capacitor grounded as close as possible to the catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy and should be somewhat isolated from the rest of the ground plane.

A ceramic input capacitor must be connected as close as possible to the VIN pin and grounded close to the GND pin. Often this capacitor is most easily located on the bottom side of the pcb. If placement close to the GND pin is not practical, the ceramic input capacitor can also be grounded close to the catch diode ground. The above layout recommendations are illustrated below in Figure 26.

It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate ground plane, shown in Figure 26 as EP GND, and in the schematics as a signal ground symbol. Both the exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in Figure 26.

The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several vias can be placed directly below the EP to increase heat flow to other layers when they are available. The recommended via hole diameter is 0.3mm.

The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away from the inductor and switch node. See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines, SNVA054, for more information regarding PCB layout for switching regulators.

10.2 Layout Example

LM26001 LM26001-Q1 20179449.gifFigure 26. Example PCB Layout

10.3 Thermal Considerations and TSD

Although the LM26001 has a built in current limit, at ambient temperatures above 80°C, device temperature rise may limit the actual maximum load current. Therefore, temperature rise must be taken into consideration to determine the maximum allowable load current.

Temperature rise is a function of the power dissipation within the device. The following equations can be used to calculate power dissipation (PD) and temperature rise, where total PD is the sum of FET switching losses, FET DC losses, drive losses, Iq, and VBIAS losses:

Equation 25. PDTOTAL = PswAC + PswDC + PQG + PIq + PVBIAS
Equation 26. LM26001 LM26001-Q1 20179450.gif
Equation 27. PswDC = D x Iload2 x (0.2 + 0.00065 x (Tj - 25))
Equation 28. PQG = Vin x 4.6 x 10-9 x fsw
Equation 29. PIq = Vin x Iq
Equation 30. PVBIAS = Vbias x IVBIAS

Given this total power dissipation, junction temperature can be calculated as follows:

Equation 31. Tj = Ta + (PDTOTAL x θJA)

Where θJA=38°C/W (typically) when using a multi-layer board with a large copper plane area. θJA varies with board type and metallization area.

To calculate the maximum allowable power dissipation, assume Tj = 125°C. To ensure that junction temperature does not exceed the maximum operating rating of 125°C, power dissipation should be verified at the maximum expected operating frequency, maximum ambient temperature, and minimum and maximum input voltage. The calculated maximum load current is based on continuous operation and may be exceeded during transient conditions.

If the power dissipation remains above the maximum allowable level, device temperature will continue to rise. When the junction temperature exceeds its maximum, the LM26001 engages Thermal Shut Down (TSD). In TSD, the part remains in a shutdown state until the junction temperature falls to within normal operating limits. At this point, the device restarts in soft-start mode.