The LV family features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage from 0 V up to 5.5 V, independent of the comparator supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower pull-up resistor values will help increase the rising edge risetime, but at the expense of increasing VOL and higher power dissipation. The risetime will be dependant on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the RC time constant and increase the risetime.
Unused open drain outputs should be left floating, or can be tied to the GND pin if floating pins are not allowed. While an individual output can typically sink up to 100 mA, the total combined current for all channels must be less than 200 mA.