JAJSCO0D データシート

JAJSCO0D November 2016 – August 2021 LM5170-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PHP|48
- MPQF051B

サーマルパッド・メカニカル・データ

PHP|48
- PPTD117D

発注情報

7.5 Electrical Characteristics

F_OSC = 100 kHz; V_VCC = 10 V; V_VIN = V_HV-Port = 48 V and V_LV-Port = 12 V, unless otherwise stated.⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN⁽³⁾	TYP⁽²⁾	MAX⁽³⁾	UNIT
VIN SUPPLY (VIN, VINX)
I_SHUTDOWN	VIN pin current in shutdown mode	V_UVLO = 0 V			10	µA
I_STANDBY	VIN pin current, no switching	V_VCC > 9 V, V_UVLO > 2.5 V, V_EN1 = V_EN2 = 0 V		1		mA
	VIN to VINX disconnect switch	V_UVLO < 1 V or V_VCC < 7.5 V	5			MΩ
	VIN to VINX disconnect switch	V_UVLO > 2.6 V, V_VCC > 9 V		100		Ω
VCC AND VCCA BIAS SUPPLIES
V_CCUVLO	VCC undervoltage detection	V_VCC falling	7.6	8	8.3	V
V_CCHYS	VCC UVLO hysteresis	V_VCC rising	8.1	8.5	8.9	V
I_{VCC_SD}	VCC sink current in shutdown mode	V_UVLO = 0 V			20	µA
I_{VCC_SB}	VCC sink current in standby: no switching	V_UVLO > 2.6 V, V_EN1 = V_EN2 = 0 V			10	mA
MASTER ON/OFF CONTROL (UVLO)
V_{UVLO_TH}	UVLO release threshold	UVLO voltage rising	2.4	2.5	2.6	V
I_HYS	UVLO hysteresis current	UVLO source current when V_UVLO > 2.6 V	21	25	29	µA
V_SD	UVLO shutdown threshold (IC shutdown)	UVLO voltage falling	1	1.25	1.5	V
	UVLO shutdown release	UVLO voltage rising above V_SD	0.15	0.25	0.35	V
t_UVLO	UVLO glitch filter time	UVLO voltage falling		2.5		µs
	UVLO internal pulldown current			1		µA
CHANNEL ENABLE INPUTS EN1 AND EN2
V_IL	Enable input low state	Disabled the driver outputs			1	V
V_IH	Enable input high state	Enable the driver outputs	2			V
	Internal pulldown impedance	EN1, EN2 internal pulldown resistor		100		kΩ
	EN glitch filter time (the rising and falling edges)			2		µs
DIRECTION COMMAND (DIR)
V_DIR	Command for current flowing from LV-Port to HV-Port (boost mode 12 V to 48 V)	Actively pulled low by external circuit			1	V
	Command for current flowing from HV-Port to LV-Port (buck mode 48 V to 12 V)	Actively pulled high by external circuit	2			V
	Standby (invalid DIR command)	DIR neither active high nor active low		1.5		V
	DIR glitch filter	Both rising and falling edges		10		µs
ISET INPUT (ISETA, ISETD)
G_ISETA	Regulated DC current sense voltage to ISETA voltage	\|V_CSA – V_CSB\| = 50 mV	19.7	20	20.3	mV/V
	ISETA internal pulldown resistor			170		kΩ
G_ISETD	Conversion ratio of ISETA voltage to ISETD duty cycle	ISETD frequency = 10 kHz, Duty = 100%	30.63	31.25	31.88	mV / %
V_{ISETD _LO}	ISETD PWM signal low-state voltage				1	V
V_{ISETD _HI}	ISETD PWM signal high-state voltage		2			V
	ISETD internal pulldown resistor			100		kΩ
	ISETD internal decoder filter resistor (tied to ISETA pin)			100		kΩ
OUTPUT CURRENT MONITOR (IOUT1, IOUT2)
G_{IOUT_BK1}	IOUT1 and IOUT2 versus channel current sense voltage, in buck mode	\|V_CSA – V_CSB\| = 50 mV, V_DIR > 2 V	4.9	5	5.1	μA/mV
G_{IOUT_BST1}	IOUT1 and IOUT2 versus channel current sense voltage, in boost mode	\|V_CSA – V_CSB\| = 50 mV, V_DIR < 1 V	4.9	5	5.1	μA/mV
G_{IOUT_BK2}	IOUT1 and IOUT2 versus channel current sense voltage, in buck mode	\|V_CSA – V_CSB\| = 10 mV, V_DIR > 2 V, T_J = 25°C	4.91	5.18	5.43	μA/mV
G_{IOUT_BST2}	IOUT1 and IOUT2 versus channel current sense voltage, in boost mode	\|V_CSA – V_CSB\| = 10 mV, V_DIR < 1 V, T_J = 25°C	4.47	4.77	5.1	μA/mV
	IOUT1 and IOUT2 DC offset currents	\|V_CSA – V_CSB\| = 0 mV	22	25	28	µA
CURRENT SENSE AMPLIFIER (BOTH CHANNELS)
G_{CS_BK1}	Amplifier output to current sense voltage in buck mode	\|V_CSA – V_CSB\| = 50 mV, V_DIR > 2 V	49.25	50	50.75	V/V
G_{CS_BST1}	Amplifier output to current sense voltage in boost mode	\|V_CSA – V_CSB\| = 50 mV, V_DIR < 1 V	49.25	50	50.75	V/V
G_{CS_BK2}	Amplifier output to current sense voltage in buck mode	\|V_CSA – V_CSB\| = 10 mV, V_DIR > 2 V, T_J = 25°C	49	52	55	V/V
G_{CS_BST2}	Amplifier output to current sense voltage in boost mode	\|V_CSA – V_CSB\| = 10 mV, V_DIR < 1 V, T_J = 25°C	45	48	51	V/V
BW_CS	Amplifier bandwidth			10		MHz
TRANSCONDUCTION AMPLIFIER (COMP1, COMP2)
Gm	Transconductance			1		mA/V
I_COMP	Output source current limit	V_ISETA = 2.5 V, \|V_CSA – V_CSB\| = 10 mV		2		mA
	Output sink current limit	V_ISETA = 0 V, \|V_CSA – V_CSB\| = 50 mV		–2		mA
BW_gm	Amplifier bandwidth			4		MHz
PWM COMPARATOR
	COMP to output delay			50		ns
	COMP to PWM offset			1		V
T_OFF(min)	Minimum OFF time		150	200	250	ns
RAMP GENERATOR (RAMP1 AND RAMP2)
	RAMP discharge device R_DS(on)				15	Ω
	Threshold voltage for valid ramp signal		0.6			V
PEAK CURRENT LIMIT (IPK)
	IPK internal current source		24.375	25	25.625	µA
IPK_Buck	Current sense voltage versus cycle-by-cycle limit threshold voltage given at IPK pin, in buck mode	R_IPK = 40 kΩ, V_DIR > 2 V	35.8	46	58.9	mV/V
IPK_Boost	Current sense voltage versus cycle-by-cycle limit threshold voltage given at IPK pin, in boost mode	R_IPK = 40 kΩ, V_DIR < 1 V	38.5	48	62.25	mV/V
OVERVOLTAGE PROTECTION (OVPA, OVPB)
	OVP threshold	OVP voltage rising	1.15	1.185	1.22	V
OVP_HYS	OVP hysteresis (falling edge)			100		mV
	OVPA and OVPB glitch filter			5		µs
R_OVPA	Internal OVPA pullup resistor	VINX to OVPA impedance		3		MΩ
R_OVPB	Internal OVPB pullup resistor	CSB1 to OVPB impedance, V_UVLO > 2.6 V		1		MΩ
OSCILLATOR (OSC)
	Oscillator frequency 1	R_OSC = 40 kΩ, SYNCIN open	90	100	110	kHz
	Oscillator frequency 2	R_OSC = 10 kΩ, SYNCIN open	335	375	410	kHz
V_OSC	OSC pin DC voltage			1.25		V
SYNCIN
V_SYNIH	SYNCIN input threshold for high state		2			V
V_{SYNIL SYNC}	SYNCIN input threshold for low state				1	V
	Internal pulldown impedance	V_SYNCIN = 2.5 V		100		kΩ
	Delay to establish synchronization	0.8 × F_OSC < F_SYNCIN < 1.2 × F_OSC		200		µs
SYNCOUT
V_SYNOH	SYNCOUT high state		2.5			V
V_SYNOL	SYNCOUT low state				0.4	V
	Sourcing current when SYNCOUT in high state	V_SYNCOUT = 2.5 V		1		mA
	SYNCOUT pulse width		240	300	370	ns
	SYNCOUT phase delay configurations	V_OPT > 2 V		90		Degree
	SYNCOUT phase delay configurations	V_OPT < 1 V		120		Degree
R_SYNCOUT	Circuit breaker signature	Use circuit breaker function and fault detection at start-up		OPEN		kΩ
R_SYNCOUT	Circuit breaker signature	Do not use circuit breaker function or disable fault detection at start-up		10		kΩ
BOOTSTRAP (HB1, HB2)
V_HB-UV	Bootstrap undervoltage threshold	(V_HB – V_SW) voltage rising	5.7	6.5	7.3	V
V_HB-UV-HYS	Hysteresis			0.5		V
I_HB-LK	Bootstrap quiescent current	V_HB – V_SW = 10 V, V_HO – V_SW = 0 V			50	µA
HIGH-SIDE GATE DRIVERS (HO1, HO2)
V_OLH	HO low-state output voltage	I_HO = 100 mA		0.1		V
V_OHH	HO high-state output voltage	I_HO = –100 mA, V_OHH = V_HB – V_HO		0.15		V
	HO rise time (10% to 90% pulse magnitude)	C_LD = 1000 pF		5		ns
	HO fall time (90% to 10% pulse magnitude)	C_LD = 1000 pF		4		ns
I_OHH	HO peak source current	V_HB – V_SW = 10 V		4		A
I_OLH	HO peak sink current	V_HB – V_SW = 10 V		5		A
LOW-SIDE GATE DRIVERS (LO1, LO2)
V_OLL	LO low-state output voltage	I_LO = 100 mA		0.1		V
V_OHL	LO high-state output voltage	I_LO = –100 mA, V_OHL = V_VCC – V_LO		0.15		V
	LO rise time (10% to 90% pulse magnitude)	C_LD = 1000 pF		5		ns
	LO fall time (90% to 10% pulse magnitude)	C_LD = 1000 pF		4		ns
I_OHL	LO peak source current			4		A
I_OLL	LO peak sink current			5		A
INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT)
V_OPTL	OPT input low state				1	V
V_OPTH	OPT input high state		2			V
	HO2 on-time rising edge versus HO1 on-time rising edge, or LO2 on-time rising edge versus LO1 on-time rising edge	V_OPT > 2 V for 2, 4, 6, and 8 phases	175	180	185	Degrees
		V_OPT < 1 V for 3 phases	235	240	245	Degrees
	Internal pulldown impedance			1		MΩ
DEAD TIME (DT)
t_DT	LO falling edge to HO rising edge delay	R_DT = 7.5 kΩ		40		ns
t_DT	HO falling edge to LO rising edge delay	R_DT = 7.5 kΩ		40		ns
V_DT	DC voltage level for programming			1.25		V
V_DT	DC voltage for adaptive dead time scheme only (short DT to VCCA)			VCCA		V
V_ADPT	HO-SW or LO-GND voltage threshold to enable cross output for adaptive dead time scheme	V_VCC > 9 V, (V_HB – V_SW) > 8 V, HO or LO voltage falling		1.5		V
t_ADPT	LO falling edge to HO rising edge delay	V_DT = V_VCC		36		ns
t_ADPT	HO falling edge to LO rising edge delay	V_DT = V_VCC		41		ns
SOFT START (SS)
I_SS	SS charging current source	V_SS = 0 V		25		µA
V_SS-OFFS	SS to PWM comparator offset	SS – PWM comparator noninverting input		1		V
R_SS	SS discharge device R_DS(on)	V_SS = 2 V		30		Ω
V_{SS_LOW}	SS discharge completion threshold	Once it is discharged by internal logic		0.23		V
DIODE EMULATION
	Current zero cross threshold	Current sense voltage		0		mV
CKT BREAKER CONTROL (BRKG, BRKS)
I_BRKG	Sourcing current	nFAULT = 5 V, V_VIN = 24 V, V_BRKS = 12 V	275	330	375	µA
V_BRK-CLP	Voltage clamp	nFAULT= 5 V, V_VIN = 48 V, V_BRKS = 12 V	9		14	V
R_BRK-SINK	Sinking capability	nFAULT = 0 V		20		Ω
V_READY	BRKG to BRKS voltage threshold to indicate readiness for operation	Rising edge	6.5	8.5		V
I_BRKG-LEAK	BRKG leakage current	nFAULT= 5 V, V_VIN – V_BRKS = 0 V, V_BRKG – V_BRKS = 10 V			10	µA
FAULT ALARM (nFAULT)
	In normal operation, no fault		4	5		V
	Internal pull-up impedance for normal operation			30		kΩ
	Internal pull-down FET R_DS(on) after fault detected				125	Ω
	External pull-down voltage threshold for IC shutdown				1	V
t_FAULT	External pul-ldown glitch filter			2		µs
t_{d1_FAULT}	Delay time of nFAULT pull-down below 1 V to (V_BRKG – V_BRKS) < 1.5 V				5	µs
t_{d2_FAULT}	Start-up fault detection duration	V_UVLO > 2.6 V, V_VCC > 9 V			3	ms
THERMAL SHUTDOWN
T_SD	Thermal shutdown			175		°C
T_SD-HYS	Thermal shutdown hysteresis			25		°C

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) Typical values correspond to T_J = 25°C.

(3) Minimum and maximum limits apply over the –40°C to 125°C junction temperature range.