JAJSM35B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External Components Selection
            1. 9.2.1.2.1.1 Input Capacitors
              1. 9.2.1.2.1.1.1 Input Capacitor Selection
            2. 9.2.1.2.1.2 Output Inductors and Capacitors Selection
              1. 9.2.1.2.1.2.1 Inductor Selection
              2. 9.2.1.2.1.2.2 Output Capacitor Selection
          2. 9.2.1.2.2 Setting the Output Voltage
            1. 9.2.1.2.2.1 FB for Adjustable Versions
          3. 9.2.1.2.3 VCC
          4. 9.2.1.2.4 BIAS
          5. 9.2.1.2.5 CBOOT
          6. 9.2.1.2.6 Maximum Ambient Temperature
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Adjustable Output
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RNL|22
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-88DCA875-A200-4333-98FA-E574F78650F4-low.gifFigure 6-1 RNL Package22-Pin VQFNTop View
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
1 VCC A Internal 3.1-V LDO output. Used as supply to internal control circuits. Connect a high-quality 4.7-µF capacitor from this pin to AGND.
2 CBOOT P Bootstrap capacitor connection for gate drivers. Connect a high quality 470-nF capacitor from this pin to the SW pin.
3 SYNC I Synchronization input to regulator. Used to synchronize the device switching frequency to a system clock. Triggers on rising edge of external clock; frequency must be in the range of 1.9 MHz and 2.3 MHz.
4 PVIN1 P Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect PVIN1 and PVIN2 pins directly together at PCB.
5, 6, 7, 8 PGND1 G Power ground to internal low side MOSFET. These pins must be tied together on the PCB. Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground.
9 SW P Regulator switch node. Connect to power inductor.
10, 11, 12, 13 PGND2 G Power ground to internal low side MOSFET. These pins must be tied together. Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground.
14 PVIN2 P Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect PVIN1 and PVIN2 pins directly together at PCB.
15 AVIN A Analog VIN, Connect to PVIN1 and PVIN2 on PCB.
16 FPWM I Do not float. Mode control input of regulator. High = FPWM, low = Automatic light load mode.
17 NC — No internal connection
18 EN I Enable input to regulator. High = on, Low = off. Can be connected to VIN. Do not float.
19 RESET O Open drain reset output flag. Connect to suitable voltage supply through a current limiting resistor. High = regulator OK, Low = regulator fault. Goes low when EN = low.
20 AGND G Analog ground for regulator and system. All electrical parameters are measured with respect to this pin. Connect to PGND on PCB
21 FB A Feedback input to regulator. Connect to output voltage node for fixed VOUT options. Connect to feedback voltage divider for adjustable option.
22 BIAS P Input to auxiliary bias regulator. Connect to output voltage node.
(1) A = Analog, O = Output, I = Input, G = Ground, P = Power