JAJSL98B October   2020  – June 2021 LMG3522R030-Q1 , LMG3525R030-Q1


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Delays
      2. 8.1.2 Turn-Off Delays
      3. 8.1.3 Drain Slew Rate
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Direct-Drive GaN Architecture
      2. 9.3.2 Drain-Source Voltage Capability
      3. 9.3.3 Internal Buck-Boost DC-DC Converter
      4. 9.3.4 VDD Bias Supply
      5. 9.3.5 Auxiliary LDO
      6. 9.3.6 Fault Detection
        1. Overcurrent Protection and Short-Circuit Protection
        2. Overtemperature Shutdown
        3. UVLO Protection
        4. Fault Reporting
      7. 9.3.7 Drive Strength Adjustment
      8. 9.3.8 Temperature-Sensing Output
      9. 9.3.9 Sync-FET Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Slew Rate Selection
          1. Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. Signal Level-Shifting
        3. Buck-Boost Converter Design
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Loop Inductance
      2. 12.1.2 Signal Ground Connection
      3. 12.1.3 Bypass Capacitors
      4. 12.1.4 Switch-Node Capacitance
      5. 12.1.5 Signal Integrity
      6. 12.1.6 High-Voltage Spacing
      7. 12.1.7 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information



  • RQS|52

Overcurrent Protection and Short-Circuit Protection

There are two types of current faults which can be detected by the driver: overcurrent fault and short-circuit fault.

The overcurrent protection (OCP) circuit monitors drain current and compares that current signal with an internally set limit. Upon detection of the overcurrent, the LMG352xR030-Q1 conducts cycle-by-cycle overcurrent protection as shown in Figure 9-3. In this mode, the GaN device is shut off when overcurrent happens, but the overcurrent signal will clear after the input PWM goes low. In the next cycle, the GaN device can turn on as normal. The cycle-by-cycle function can be used in cases where steady-state operation current is below the OCP level but transient response can still reach current limit, while the circuit operation cannot be paused. It also prevents the GaN device from overheating by having overcurrent induced conduction loss.

The short-circuit protection (SCP) monitors drain current and compares that current signal with a internally set limit higher than that of OCP as shown in Figure 9-4. It is designed to protect the GaN device from high-current short-circuit fault. When SCP happens at high current, the driver is intentionally slowed down to obtain lower di/dt. Therefore, lower overshoot voltage and ringing can be achieved during the turn-off event.On detection of the overcurrent, LMG352xR030-Q1 conduct latched turn-off. This fast response circuit could protect the GaN device even under a hard short-circuit condition. In this protection, the GaN device is shut off and held off until the fault is reset by either holding the IN pin low for a period of time defined in Section 7 or removing power from VDD.

During OCP or SCP in a half bridge, after the current reaches the upper limit and the device is turned off by protection, the PWM input of the device could still be high and the PWM input of the complementary device could still be low. In this case, the load current can flow through the third quadrant of the complementary device with no synchronous rectification. The extra high negative voltage drop (–6 V to –8 V) from drain to source could lead to high third-quadrant loss, similar to dead time loss but with much longer time. Section 9.3.9 offers adaptive dead time and reduces third-quadrant loss.

For safety considerations, OCP allows cycle-by-cycle operation while SCP will latch the device until reset. By reading the FAULT and OC pins, the exact current fault type can be determined. Refer to Section for detailed information.

GUID-20201021-CA0I-GQM5-M99W-DHLQ1HKKL8XJ-low.gifFigure 9-3 Cycle-by-Cycle OCP Operation
GUID-6636DAE2-B4A2-45C9-B2C4-5F74AA08AD40-low.gifFigure 9-4 Overcurrent Detection vs. Short-Circuit Detection