SNAS674B September   2015  – February 2017 LMK61E2


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 ADD Input Characteristics
    11. 6.11 Frequency Tolerance Characteristics
    12. 6.12 Power-On/Reset Characteristics (VDD)
    13. 6.13 I2C-Compatible Interface Characteristics (SDA, SCL)
    14. 6.14 PSRR Characteristics
    15. 6.15 Other Characteristics
    16. 6.16 PLL Clock Output Jitter Characteristics
    17. 6.17 Typical 156.25-MHz Output Phase Noise Characteristics
    18. 6.18 Typical 161.1328125 MHz Output Phase Noise Characteristics
    19. 6.19 Additional Reliability and Qualification
    20. 6.20 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Circuitry
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 EEPROM Map
    7. 8.7 Register Map
      1. 8.7.1 Register Descriptions
        1.  VNDRID_BY1 Register; R0
        2.  VNDRID_BY0 Register; R1
        3.  PRODID Register; R2
        4.  REVID Register; R3
        5.  SLAVEADR Register; R8
        6.  EEREV Register; R9
        7.  DEV_CTL Register; R10
        8.  XO_CAPCTRL_BY1 Register; R16
        9.  XO_CAPCTRL_BY0 Register; R17
        10. DIFFCTL Register; R21
        11. OUTDIV_BY1 Register; R22
        12. OUTDIV_BY0 Register; R23
        13. PLL_NDIV_BY1 Register; R25
        14. PLL_NDIV_BY0 Register; R26
        15. PLL_FRACNUM_BY2 Register; R27
        16. PLL_FRACNUM_BY1 Register; R28
        17. PLL_FRACNUM_BY0 Register; R29
        18. PLL_FRACDEN_BY2 Register; R30
        19. PLL_FRACDEN_BY1 Register; R31
        20. PLL_FRACDEN_BY0 Register; R32
        21. PLL_MASHCTRL Register; R33
        22. PLL_CTRL0 Register; R34
        23. PLL_CTRL1 Register; R35
        24. PLL_LF_R2 Register; R36
        25. PLL_LF_C1 Register; R37
        26. PLL_LF_R3 Register; R38
        27. PLL_LF_C3 Register; R39
        28. PLL_CALCTRL Register; R42
        29. NVMSCRC Register; R47
        30. NVMCNT Register; R48
        31. NVMCTL Register; R49
        32. MEMADR Register; R51
        33. NVMDAT Register; R52
        34. RAMDAT Register; R53
        35. NVMUNLK Register; R56
        36. INT_LIVE Register; R66
        37. SWRST Register; R72
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Jitter Considerations in Serdes Systems
      2. 9.2.2 Frequency Margining
        1. Fine Frequency Margining
        2. Coarse Frequency Margining
      3. 9.2.3 Design Requirements
        1. Detailed Design Procedure
          1. Custom Design With WEBENCH® Tools
          2. Device Selection
          3. VCO Frequency Calculation
          4. Device Configuration
          5. PLL Loop Filter Design
          6. Spur Mitigation Techniques
            1. Phase Detection Spur
            2. Integer Boundary Fractional Spur
            3. Primary Fractional Spur
            4. Sub-Fractional Spur
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information



Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LMK61E2 is an ultra-low jitter programmable oscillator that can be used to provide reference clocks for high-speed serial links resulting in improved system performance. The LMK61E2 also supports a variety of features that aids the hardware designer during the system debug and validation phase.

Typical Applications

Jitter Considerations in Serdes Systems

Jitter-sensitive applications such as 10-Gbps or 100-Gbps Ethernet, deploy a serial link using a Serializer in the transmit section (TX) and a De-serializer in the receive section (RX). These SERDES blocks are typically embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of the TX PLL bandwidth and the RX CDR bandwidth.

As can be seen in Figure 32, the pass band region between the TX low-pass cutoff and RX high-pass cutoff frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification that needs to be met, as related to the RX CDR bandwidth.

The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example, IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10-Gbps Ethernet should be no more than 0.28 × UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter.

The jitter contributing elements are made up of the reference clock, generated potentially from a device like LMK61E2, the transmit medium, transmit driver, and so forth. Only a portion of the overall allowable transmit jitter is allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter, for a 20% clock jitter budget, is 5.43 ps, p-p.

Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern fanout buffers have low-additive random jitter (less than 100 fs RMS) with no substantial contribution to the deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For serial link systems that need to meet a bit error rate (BER) of 10–12, the allowable random jitter in root-mean-square is 0.29 ps RMS. This is calculated by dividing the p-p jitter by 14 for a BER of 10–12. Accounting for random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps RMS. This is calculated by the root-mean-square subtraction from the desired jitter at the fanout buffer's output assuming 100 fs RMS of additive jitter from the fanout buffer.

With careful frequency planning techniques, like spur optimization (covered in Spur Mitigation Techniques ) and on-chip LDOs to suppress supply noise, the LMK61E2 is able to generate clock outputs with deterministic jitter that is below 1 ps, p-p and random jitter that is below 0.2 ps RMS. This gives the serial link system with additional margin on the allowable transmit jitter resulting in a BER better than 10–12.

LMK61E2 dependence_of_clock_jitter_serial_links_snas674.gif Figure 32. Dependence of Clock Jitter in Serial Links

Frequency Margining

Fine Frequency Margining

IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock compensation.

To prevent such overflow and underflow errors from occurring, modern ASICs and FGPAs include a clock compensation scheme that introduces elastic buffers. Such a system, shown in Figure 33, is validated thoroughly during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3. The LMK61E2 provides the ability to fine tune the frequency of its outputs based on changing its load capacitance for the integrated oscillator. This fine tuning can be done through I2C as described in Integrated Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E2 undergoes a smooth monotonic change in frequency.

Coarse Frequency Margining

Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%. The LMK61E2 offers the ability to change its output divider for the desired change from its nominal output frequency as explained in the High-Speed Output Divider section.

LMK61E2 system_implementation_clock_compensation_snas674.gif Figure 33. System Implementation With Clock Compensation for Standards Compliance

Design Requirements

Consider a typical wired communications application, like a top-of-rack switch, which needs to clock high data rate 10-Gbps or 100-Gbps Ethernet PHYs. In such systems, the clock is expected to be available upon power up without the need for any device-level programming. An example of such a clock frequency would be a 156.25 MHz in LVPECL output format.

The Detailed Design Procedure below describes the detailed design procedure to generate the required output frequencies for the above scenario using LMK61E2.

Detailed Design Procedure

Design of all aspects of the LMK61E2 is simplified with software support that assists in part selection, part programming, loop filter design, and phase noise simulation. This design procedure will give a quick outline of the process.

  1. Device Selection
    • The first step to calculate the specified VCO frequency given required output frequency. The device must be able to produce the VCO frequency that can be divided down to the required output frequency.
    • The WEBENCH Clock Architect Tool from TI will aid in the selection of the right device that meets the customer's output frequency and format requirements.
  2. Device Configuration
    • There are many device configurations to achieve the desired output frequency from a device. However, the user should consider some optimizations and trade-offs.
    • The WEBENCH Clock Architect Tool attempts to maximize the phase detector frequency, use smallest dividers, and maximizes PLL charge pump current.
    • These guidelines below may be followed when configuring PLL related dividers or other related registers:
      • For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
      • For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge pump currents often have similar performance due to diminishing returns.
      • For fractional divider values, keep the denominator at highest value possible in order to minimize spurs. It is also best to use higher order modulator wherever possible for the same reason.
      • As a rule of thumb, keeping the phase detector frequency approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be unstable and a phase.
  3. PLL Loop Filter Design
    • It is recommended to use the WEBENCH Clock Architect Tool to design your loop filter.
    • Optimal loop filter design and simulation can be achieved when custom reference phase noise profiles are loaded into the software tool.
    • While designing the loop filter, adjusting the charge pump current or N value can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller component values but may increase impacts of leakage and reduce PLL phase noise performance.
    • For a more detailed understanding of loop filter design can be found in PLL Performance, Simulation, and Design (SNAA106).
  4. Device Programming
    • The EVM programming software tool CodeLoader can be used to program the device with the desired configuration.

Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMK61E2 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at

Device Selection

Use the WEBENCH Clock Architect Tool. Enter the required output frequencies and formats into the tool. To use this device, find a solution using the LMK61E2.

VCO Frequency Calculation

In this example, the VCO frequency of the LMK61E2 to generate 156.25 MHz can be calculated as 5 GHz.

Device Configuration

For this example, enter the desired output frequency and click on Generate Solutions. Select LMK61E2 from the solution list. From the simulation page of the WEBENCH Clock Architect Tool, it can be seen that to maximize phase detector frequency, PLL R divider is set to 1, doubler is enabled and N divider is set to 50 for a PFD frequency of 100 MHz. This results in a VCO frequency of 5 GHz. At this point the design meets the output frequency requirements and it is possible to design a loop filter for system and simulate performance on the clock output.

PLL Loop Filter Design

In the WEBENCH Clock Architect Tool simulator, click on the PLL loop filter design button, then press recommend design. For the PLL loop filter, maximum phase detector frequency and maximum charge pump current are typically used. The tool recommends a loop filter that is designed to minimize jitter. The integrated loop filter’s components are minimized with this recommendation as to allow maximum flexibility in achieving wide loop bandwidths for low PLL noise. With the recommended loop filter calculated, this loop filter is ready to be simulated.

The PLL loop filter’s bode plot can additionally be viewed and adjustments can be made to the integrated components. The effective loop bandwidth and phase margin with the updated values is then calculated. The integrated loop filter components are good to use when attempting to eliminate certain spurs. The recommended procedure is to increase C3 capacitance, then R3 resistance. Large R3 resistance can result in degraded VCO phase noise performance.

Spur Mitigation Techniques

The LMK61E2 offers several programmable features for optimizing fractional spurs. In order to get the best out of these features, it makes sense to understand the different kinds of spurs as well as their behaviors, causes, and remedies. Although optimizing spurs may involve some trial and error, there are ways to make this process more systematic. TI offers the Clock Design Tool for more information and estimation of fractional spurs.

Phase Detection Spur

The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, fPD. To minimize this spur, a lower phase detector frequency should be considered. In some cases where the loop bandwidth is very wide relative to the phase detector frequency, some benefit might be gained from using a narrower loop bandwidth or adding poles to the loop filter by using R3 and C3 if previously unused, but otherwise the loop filter has minimal impact. Bypassing at the supply pins and board layout can also have an impact on this spur, especially at higher phase detector frequencies.

Integer Boundary Fractional Spur

This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency is 5003 MHz, then the integer boundary spur would be at 3-MHz offset. This spur can be either PLL or VCO dominated. If it is PLL dominated, decreasing the loop bandwidth and some of the programmable fractional words may impact this spur. If the spur is VCO dominated, then reducing the loop filter will not help, but rather reducing the phase detector and having good slew rate and signal integrity at the selected reference input will help.

Primary Fractional Spur

These spurs occur at multiples of fPD/DEN and are not the integer boundary spur. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at 1 MHz, 2 MHz, 4 MHz, 5 MHz, 6 MHz, and so forth. These are impacted by the loop filter bandwidth and modulator order. If a small frequency error is acceptable, then a larger equivalent fraction may improve these spurs. This larger unequivalent fraction pushes the fractional spur energy to much lower frequencies that where they are not impactful to the system performance.

Sub-Fractional Spur

These spurs appear at a fraction of fPD/DEN and depend on modulator order. With the first order modulator, there are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if the denominator is even. A third order modulator can produce sub-fractional spurs at 1/2, 1/3, or 1/6 of the offset, depending if it is divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, no sub-fractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a second or third order modulator would be expected. Aside from strategically choosing the fractional denominator and using a lower order modulator, another tactic to eliminate these spurs is to use dithering and express the fraction in larger equivalent terms. Because dithering also adds phase noise, its level needs to be managed to achieve acceptable phase noise and spurious performance.

Table 2 summarizes spur and mitigation techniques.

Table 2. Spur and Mitigation Techniques

Phase Detector fPD Reduce Phase Detector Frequency. Although reducing the phase detector frequency does improve this spur, it also degrades phase noise.
Integer Boundary fVCO mod fPD Methods for PLL Dominated Spurs Reducing the loop bandwidth may degrade the total integrated noise if the bandwidth is too narrow.
-     Avoid the worst case VCO frequencies if possible.
-     Ensure good slew rate and signal integrity at reference input.
-     Reduce loop bandwidth or add more filter poles to suppress out of band spurs.
Methods for VCO Dominated Spurs Reducing the phase detector may degrade the phase noise.
-     Avoid the worst case VCO frequencies if possible.
-     Reduce Phase Detector Frequency.
-     Ensure good slew rate and signal integrity at reference input.
Primary Fractional fPD/DEN -     Decrease Loop Bandwidth. Decreasing the loop bandwidth may degrade in-band phase noise. Also, larger unequivalent fractions don’t always reduce spurs.
-     Change Modulator Order.
-     Use Larger Unequivalent Fractions.
Sub-Fractional fPD/DEN/k k=2,3, or 6 -     Use Dithering. Dithering and larger fractions may increase phase noise.
-     Use Larger Equivalent Fractions.
-     Use Larger Unequivalent Fractions.
-     Reduce Modulator Order.
-     Eliminate factors of 2 or 3 in denominator.