The power-good feature using the PGOOD pin of the LMR436x0-Q1 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 8-8. Table 8-3 gives a more detailed breakdown of the PGOOD operation. Here, VPGDUV is defined as the PGDUV scaled version of VOUT (target regulated output voltage) and VPGDHYST as the PGDHYST scaled version of VOUT, where both PGDUV and PGDHYST are listed in Section 7.5. During the initial power up, a total delay of 6 ms (typical) is encountered from the time VEN-VOUT is triggered to the time that the power-good is flagged high. This delay only occurs during the device start-up and is not encountered during any other normal operation of the power-good function. When EN is pulled low, the power-good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage (VPGD-VAL is ≥ 1.5 V (max)).
The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit the current into this pin to ≤ 4 mA.
|FAULT CONDITION INITIATED||FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)|
|VOUT < VPGDUV AND t > tRESET_FILTER||Output voltage in regulation: |
VPGDUV + VPGDHYST < VOUT < VPGDOV - VPGDHYST
|VOUT > VPGDOV AND t > tRESET_FILTER||Output voltage in regulation|
|TJ > TSD(trip)||TJ < TSD(trip)-TSD(hyst) AND output voltage in regulation|
|EN < VEN-VOUT - VEN-HYST||EN > VEN-VOUT AND output voltage in regulation|