JAJSE59A October   2017  – June 2022 LMT87-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Accuracy Characteristics
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LMT87-Q1 Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mounting and Thermal Conductivity
      2. 8.4.2 Output Noise Considerations
      3. 8.4.3 Capacitive Loads
      4. 8.4.4 Output Voltage Shift
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Connection to ADC
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Conserving Power Dissipation With Shutdown
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics

Unless otherwise noted, these specifications apply for +VDD = 2.7 V to 5.5 V. MIN and MAX limits apply for TA = TJ = TMIN to TMAX ; typical limits apply for TA = TJ = 25°C.
PARAMETERTEST CONDITIONSMIN(2)TYP (1)MAX (2)UNIT
Sensor gain (output transfer function slope)–13.6mV/°C
Load regulation(3)Source ≤ 50 μA, (VDD – VOUT) ≥ 200 mV–1–0.22mV
Sink ≤ 50 μA, VOUT ≥ 200 mV0.261mV
Line regulation(4)200μV/V
ISSupply currentTA = 30°C to 150°C, (VDD – VOUT) ≥ 100 mV5.48.1μA
TA = –50°C to 150°C, (VDD – VOUT) ≥ 100 mV5.49μA
CLOutput load capacitance1100pF
Power-on time(5)CL= 0 pF to 1100 pF0.71.9ms
Output driveTA = TJ = 25°C–5050μA
(1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(2) Limits are specific to TI's AOQL (Average Outgoing Quality Level).
(3) Source currents are flowing out of the LMT87-Q1. Sink currents are flowing into the LMT87-Q1.
(4) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Section 8.4.4.
(5) Specified by design and characterization.