JAJSDN8C March 2017 – April 2019 LMX2594
The state machine clock is a divided down version of the OSCin signal that is used internally in the device. This divide value is 1, 2, 4, or 8, and is determined by CAL_CLK_DIV programming word (described in the Programming section). This state machine clock impacts various features like the lock detect delay, VCO calibration, and ramping. The state machine clock is calculated as fsmclk = fOSC / 2CAL_CLK_DIV.