JAJSB13S December 2009 – July 2017 LMZ14203

PRODUCTION DATA.

- 1 特長
- 2 アプリケーション
- 3 概要
- 4 改訂履歴
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11デバイスおよびドキュメントのサポート
- 12メカニカル、パッケージ、および注文情報

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

The LMZ14203 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select components for the LMZ14203. Alternately, the WEBENCH software may be used to generate complete designs.

When generating a design, the WEBENCH software uses iterative design procedure and accesses comprehensive databases of components. For more details, see www.ti.com.

For this example the following application parameters exist.

- V
_{IN}Range = Up to 42 V - V
_{OUT}= 0.8 V to 5 V - I
_{OUT}= 3 A

Please refer to Table 1 for more information.

VOUT (V) | R_{FBT} (kΩ) |
R_{FBB} (kΩ) |
R_{DS(on)} (kΩ) |
VIN (V) | |
---|---|---|---|---|---|

MIN | MAX | ||||

5 | 5.62 | 1.07 | 100 | 7.5 | 42 |

3.3 | 3.32 | 61.9 | 6 | 42 | |

2.5 | 2.26 | 47.5 | 30 | ||

1.8 | 1.87 | 1.5 | 32.4 | 25 | |

1.5 | 1 | 1.13 | 28 | 21 | |

1.2 | 4.22 | 8.45 | 22.6 | 19 | |

0.8 | 0 | 39.2 | 24.9 | 18 |

Ref Des | Description | Case Size | Manufacturer | Manufacturer P/N |
---|---|---|---|---|

U1 | SIMPLE SWITCHER | PFM-7 | Texas Instruments | LMZ14203TZ |

C_{IN1} |
1 µF, 50 V, X7R | 1206 | Taiyo Yuden | UMK316B7105KL-T |

C_{IN2} |
10 µF, 50 V, X7R | 1210 | Taiyo Yuden | UMK325BJ106MM-T |

C_{O1} |
1 µF, 50 V, X7R | 1206 | Taiyo Yuden | UMK316B7105KL-T |

C_{O2} |
100 µF, 6.3 V, X7R | 1210 | Taiyo Yuden | JMK325BJ107MM-T |

R_{FBT} |
3.32 kΩ | 0603 | Vishay Dale | CRCW06033K32FKEA |

R_{FBB} |
1.07 kΩ | 0603 | Vishay Dale | CRCW06031K07FKEA |

R_{ON} |
61.9 kΩ | 0603 | Vishay Dale | CRCW060361k9FKEA |

R_{ENT} |
68.1 kΩ | 0603 | Vishay Dale | CRCW060368k1FKEA |

R_{ENB} |
11.8 kΩ | 0603 | Vishay Dale | CRCW060311k8FKEA |

C_{FF} |
22 nF, ±10%, X7R, 16 V | 0603 | TDK | C1608X7R1H223K |

C_{SS} |
22 nF, ±10%, X7R, 16 V | 0603 | TDK | C1608X7R1H223K |

Click here to create a custom design using the LMZ14203 device with the WEBENCH® Power Designer.

- Start by entering the input voltage (V
_{IN}), output voltage (V_{OUT}), and output current (I_{OUT}) requirements. - Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
- Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

- Run electrical simulations to see important waveforms and circuit performance
- Run thermal simulations to understand board thermal performance
- Export customized schematic and layout into popular CAD formats
- Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

The LMZ14203 is fully supported by WEBENCH and offers the following: Component selection, electrical and thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be used to manually design the LMZ14203 application.

- Select minimum operating V
_{IN}with enable divider resistors - Program V
_{O}with divider resistor selection - Program turnon time with soft-start capacitor selection
- Select C
_{O} - Select C
_{IN} - Set operating frequency with R
_{ON} - Determine module dissipation
- Lay out PCB for required thermal performance

The enable input provides a precise 1.18-V band-gap rising threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as V_{IN}. The enable input also incorporates 90 mV (typical) of hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V. For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to limit this voltage.

The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable under voltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power-up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems such as 24-V AC/DC systems where a lower boundary of operation should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14203 output rail. The two resistors should be chosen based on the following ratio:

Equation 1. R_{ENT} / R_{ENB} = (V_{IN UVLO} / 1.18 V) – 1

The LMZ14203 demonstration and evaluation boards use 11.8 kΩ for R_{ENB} and 68.1 kΩ for R_{ENT} resulting in a rising UVLO of 8 V. This divider presents 6.25 V to the EN input when the divider input is raised to 42 V.

The EN pin is internally pulled up to VIN and can be left floating for always-on operation.

Output voltage is determined by a divider of two resistors connected between V_{O} and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ON-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at FB is above 0.8 V, ON-time cycles will not occur.

The regulated output voltage determined by the external divider resistors R_{FBT} and R_{FBB} is:

Equation 2. V_{O} = 0.8 V × (1 + R_{FBT} / R_{FBB})

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

Equation 3. R_{FBT} / R_{FBB} = (V_{O} / 0.8 V) - 1

These resistors should be chosen from values in the range of 1 kΩ to 10 kΩ.

For V_{O} = 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains that draws more than 20 uA. Converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation when no load is present.

A feed-forward capacitor is placed in parallel with R_{FBT} to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple.

A table of values for R_{FBT} , R_{FBB} , C_{FF} and R_{ON} is included in the applications schematic.

Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.

Upon turnon, after all UVLO conditions have been passed, an internal 8-uA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:

Equation 4. t_{SS} = V_{REF} × C_{SS} / Iss = 0.8 V × C_{SS} / 8 uA

This equation can be rearranged as follows:

Equation 5. C_{SS} = t_{SS} × 8 μA / 0.8 V

Use of a 0.022-μF capacitor results in 2.2 ms soft-start duration. This is recommended as a minimum value.

As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. The soft-start capacitor continues charging until it reaches approximately 3.8 V on the SS pin. Voltage levels between 0.8 V and 3.8 V have no effect on other circuit operation. Note the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200-μA current sink.

- The enable input being
*pulled low* - Thermal shutdown condition
- Overcurrent fault
- Internal V
_{CC}UVLO (Approx 4-V input to V_{IN})

None of the required C_{O} output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst case minimum ripple current rating of 0.5 × I_{LR P-P}, as calculated in Equation 12 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 SNVA422 for more detail.

The following equation provides a good first pass approximation of C_{O} for load transient requirements:

Equation 6. C_{O} ≥ I_{STEP} × V_{FB} × L × V_{IN} / (4 × V_{O} × (V_{IN} – V_{O}) × V_{OUT-TRAN})

Solving:

Equation 7. C_{O} ≥ 3 A × 0.8 V × 6.8 μH × 24 V / (4 × 3.3 V × ( 24 V – 3.3 V) × 33 mV) ≥ 43 μF

The LMZ14203 demonstration and evaluation boards are populated with a 100-uF 6.3-V X5R output capacitor. Locations for extra output capacitors are provided.

The LMZ14203 module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance should be very close to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by the equation:

Equation 8. I(C_{IN(RMS)}) ≊ 1 /2 × I_{O} × √(D / 1 – D)

where

- D ≊ V
_{O}/ V_{IN}

(As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when V_{IN} = 2 × V_{O}).

Recommended minimum input capacitance is 10uF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and temperature deratings of the capacitor selected. Note ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may need to contact the capacitor manufacturer for this rating.

If the system design requires a certain minimum value of input ripple voltage ΔV_{IN} be maintained then the following equation may be used.

If ΔV_{IN} is 1% of V_{IN} for a 24-V input to 3.3-V output application this equals 240 mV and f_{SW} = 400 kHz.

C_{IN}≥ 3 A × 3.3 V / 24 V × (1– 3.3 V / 24 V) / (400000 × 0.240 V)

≥ 3.7 μF

Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines.

Operating frequency in DCM can be calculated as follows:

Equation 10. f_{SW(DCM)} ≊ V_{O} × (V_{IN}-1) × 6.8 μH × 1.18 × 10^{20} × I_{O}/ ((V_{IN}–V_{O}) × R_{ON}^{2})

In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can be calculated using Equation 7 above.

Following is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.

The approximate formula for determining the DCM/CCM boundary is as follows:

Equation 11. I_{DCB} ≊ V_{O} × (V_{IN}– V_{O}) / (2 × 6.8 μH × f_{SW(CCM)} × V_{IN})

Following is a typical waveform showing the boundary condition.

The inductor internal to the module is 6.8 μH. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (I_{LR}). I_{LR} can be calculated with:

Equation 12. I_{LR P-P }= V_{O} × (V_{IN}– V_{O}) / (6.8µH × f_{SW} × V_{IN})

where

- V
_{IN}is the maximum input voltage and f_{SW}is determined from Equation 13.

If the output current I_{O} is determined by assuming that I_{O} = I_{L}, the higher and lower peak of I_{LR} can be determined. Be aware that the lower peak of I_{LR} must be positive if CCM operation is required.

Many designs will begin with a desired switching frequency in mind. For that purpose the following equation can be used.

Equation 13. f_{SW(CCM)} ≊ V_{O} / (1.3 × 10^{-10} × R_{ON})

This can be rearranged as

Equation 14. R_{ON} ≊ V_{O} / (1.3 × 10 ^{-10} × f_{SW(CCM)})

The selection of RON and f_{SW(CCM)} must be confined by limitations in the ON-time and OFF-time for the *COT Control Circuit Overview* section.

The ON-time of the LMZ14203 timer is determined by the resistor R_{ON} and the input voltage V_{IN}. It is calculated as follows:

Equation 15. t_{ON} = (1.3 × 10^{-10} × R_{ON}) / V_{IN}

The inverse relationship of t_{ON} and V_{IN} gives a nearly constant switching frequency as V_{IN} is varied. R_{ON} should be selected such that the ON-time at maximum V_{IN} is greater than 150 ns. The ON-timer has a limiter to ensure a minimum of 150 ns for t_{ON}. This limits the maximum operating frequency, which is governed by the following equation:

Equation 16. f_{SW(MAX)} = V_{O} / (V_{IN(MAX)} × 150 ns)

This equation can be used to select R_{ON} if a certain operating frequency is desired so long as the minimum ON-time of 150 ns is observed. The limit for R_{ON} can be calculated as follows:

Equation 17. R_{ON} ≥ V_{IN(MAX)} × 150 ns / (1.3 × 10 ^{-10})

If R_{ON} calculated in Equation 14 is less than the minimum value determined in Equation 17 a lower frequency should be selected. Alternatively, V_{IN(MAX)} can also be limited to keep the frequency unchanged.

NOTE

The minimum OFF-time of 260 ns limits the maximum duty ratio. Larger R_{ON} (lower F_{SW}) should be selected in any application requiring large duty ratio.