SNVS323I December   2004  – February 2016 LP38690-ADJ , LP38692-ADJ

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Foldback Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin (LP38692-ADJ Only)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reverse Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting The Output Voltage
        2. 8.2.2.2 External Capacitors
          1. 8.2.2.2.1 Input Capacitor
          2. 8.2.2.2.2 Output Capacitor
          3. 8.2.2.2.3 Selecting A Capacitor
            1. 8.2.2.2.3.1 Ceramic
            2. 8.2.2.2.3.2 Tantalum
        3. 8.2.2.3 RFI/EMI Susceptibility
        4. 8.2.2.4 Output Noise
        5. 8.2.2.5 Power Dissipation
        6. 8.2.2.6 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

see (1)(2)
MIN MAX UNIT
All pins (with respect to GND), VMAX –0.3 12 V
IOUT(4) Internally Limited
Power dissipation(3) Internally Limited
Junction temperature −40 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.
(3) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). When using the WSON package, refer to Leadless Leadframe Package (LLP) (SNOA401) and the WSON Mounting section in this datasheet. If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal shutdown.
(4) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
Supply voltage, VIN 2.7 10 V
Operating junction temperature, TJ –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LP38692-ADJ LP3869x-ADJ UNIT
NDC (SOT-223) NGG (WSON)
5 PINS 6 PINS
RθJA(2) Junction-to-ambient thermal resistance, High-K 68.5 50.6(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.2 44.4 °C/W
RθJB Junction-to-board thermal resistance 13.0 24.9 °C/W
ψJT Junction-to-top characterization parameter 5.5 0.4 °C/W
ψJB Junction-to-board characterization parameter 12.8 25.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 5.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Thermal resistance value RθJA is based on EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON (NGG) package RθJA includes four (4) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.

6.5 Electrical Characteristics

Unless otherwise specified: typical limits are for TJ = 25°C, minimum and maximum limits apply over the full operating temperature range; VIN = VOUT + 1 V , CIN = COUT = 10 µF, ILOAD = 10 mA. Minimum and maximum limits are specified through testing, statistical correlation, or design.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VADJ ADJ pin voltage VIN = 2.7 V, TJ = 25°C 1.219 1.25 1.281 V
3.2 V ≤ VIN ≤ 10 V
100 µA < ILOAD < 1 A		 1.187 1.25 1.313
ΔVOUT/ΔVIN Output voltage line regulation(2) VOUT + 0.5 V ≤ VIN ≤ 10 V
ILOAD = 25 mA		 0.03 0.1 %/V
ΔVOUT/ΔILOAD Output voltage load regulation(3) 1 mA < ILOAD < 1 A
VIN = VOUT + 1 V		 1.8 5 %/A
VIN – VOUT Dropout voltage(4) VOUT = 1.8 V, ILOAD = 1 A 950 1600 mV
VOUT = 2.5 V, ILOAD = 0.1 A 80 145
VOUT = 2.5 V, ILOAD = 1A 800 1300
VOUT = 3.3 V, ILOAD = 0.1 A 65 110
VOUT = 3.3 V, ILOAD = 1 A 650 1000
VOUT = 5 V, ILOAD = 0.1 A 45 100
VOUT = 5 V, ILOAD = 1 A 450 800
IQ Quiescent current VIN ≤ 10 V, ILOAD = 100 µA – 1A 55 100 µA
VEN ≤ 0.4 V, TJ = 25°C
(LP38692-ADJ Only)		 0.001 1
IL(MIN) Minimum load current VIN – VOUT ≤ 4 V 100 µA
IFB Foldback current limit VIN – VOUT > 5 V 450 mA
VIN – VOUT < 4 V 1500
PSRR Ripple rejection VIN = VOUT + 2 V(DC), with 1 V(p-p) / 120-Hz ripple 55 dB
TSD Thermal shutdown activation
(junction temperature)		 160 °C
TSD (HYST) Thermal shutdown hysteresis
(junction temperature)		 10 °C
IADJ ADJ input leakage current VADJ = 0 –1.5 V
VIN = 10 V, TJ = 25°C		 –100 0.01 100 nA
en Output noise BW = 10 Hz to 10 kHz
VOUT = 3.3 V		 0.7 µV/√Hz
VOUT (LEAK) Output leakage current VOUT = VOUT(NOM) + 1 V at 10 VIN
TJ = 25°C		 0.5 2 µA
VEN Enable voltage (LP38692-ADJ Only) Output = OFF 0.4 V
Output = ON, VIN = 4 V 1.8
Output = ON, VIN = 6 V 3
Output = ON, VIN = 10 V 4
IEN Enable pin leakage (LP38692-ADJ Only) VEN = 0 V or 10 V , VIN = 10 V
TJ = 25°C		 –1 0.001 1 µA
(1) Typical numbers represent the most likely parametric norm for 25°C operation.
(2) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(3) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1 mA to full load.
(4) Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100 mV of nominal value.

6.6 Typical Characteristics

Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, EN pin is tied to VIN (LP38692-ADJ only), VOUT = 1.25 V, VIN = 2.7 V, ILOAD = 10 mA.
LP38690-ADJ LP38692-ADJ 20126735.gif Figure 1. Noise vs Frequency
LP38690-ADJ LP38692-ADJ 20126737.gif Figure 3. Noise vs Frequency
LP38690-ADJ LP38692-ADJ 20126719.gif Figure 5. Ripple Rejection
LP38690-ADJ LP38692-ADJ 20126730.gif Figure 7. VADJ vs Temperature
LP38690-ADJ LP38692-ADJ 20126724.gif Figure 9. Line Transient Response
LP38690-ADJ LP38692-ADJ 20126726.gif Figure 11. Line Transient Response
LP38690-ADJ LP38692-ADJ 20126728.gif Figure 13. Line Transient Response
LP38690-ADJ LP38692-ADJ 20126741.gif Figure 15. Load Transient Response
LP38690-ADJ LP38692-ADJ 20126743.gif Figure 17. Load Transient Response
LP38690-ADJ LP38692-ADJ 20126758.png
VOUT = 1.25 V
Figure 19. VOUT vs VIN
LP38690-ADJ LP38692-ADJ 20126760.png Figure 21. VOUT vs VIN (Power-Up)
LP38690-ADJ LP38692-ADJ 20126751.gif Figure 23. Dropout Voltage vs IOUT
LP38690-ADJ LP38692-ADJ 20126754.gif Figure 25. Load Regulation vs Temperature
LP38690-ADJ LP38692-ADJ 20126736.gif Figure 2. Noise vs Frequency
LP38690-ADJ LP38692-ADJ 20126717.gif Figure 4. Ripple Rejection
LP38690-ADJ LP38692-ADJ 20126721.gif Figure 6. Ripple Rejection
LP38690-ADJ LP38692-ADJ 20126723.gif Figure 8. Line Transient Response
LP38690-ADJ LP38692-ADJ 20126725.gif Figure 10. Line Transient Response
LP38690-ADJ LP38692-ADJ 20126727.gif Figure 12. Line Transient Response
LP38690-ADJ LP38692-ADJ 20126740.gif Figure 14. Load Transient Response
LP38690-ADJ LP38692-ADJ 20126742.gif Figure 16. Load Transient Response
LP38690-ADJ LP38692-ADJ 20126744.gif Figure 18. Load Transient Response
LP38690-ADJ LP38692-ADJ 20126759.png
VOUT = 1.8 V
Figure 20. VOUT vs VIN
LP38690-ADJ LP38692-ADJ 20126750.gif Figure 22. Minimum VIN vs IOUT
LP38690-ADJ LP38692-ADJ 20126753.gif Figure 24. Enable Voltage vs Temperature
LP38690-ADJ LP38692-ADJ 20126755.gif Figure 26. Line Regulation vs Temperature