A power rail output error occurs when an error condition is detected from the output rails of the device that are used to power the attached MCU or SoC. These errors include the following:

• Rails not reaching or maintaining within the power good voltage level threshold.
• A short condition that is detected at a regulator output.
• The load current that exceeds the forward current limit.

The BUCKn_GRP_SEL, VMONn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or other rail group. The LP8764-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups.

Figure 8-4 shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] registers are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0], any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power cycled.

The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in Figure 8-6, when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals LP8764-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to Section 8.4.2.4.2.1 for information regarding the setting of the NSLEEP1 and NSLEEP2 signals.