JAJSO71 March 2022 LP8764-Q1
PRODUCTION DATA
The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories:
All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host.
Some of the interrupts and EN_DRV status are also sent to host during SPI communication. See Section 8.11.3 for more information on SPI status signals.
Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs.
More detail descriptions of each interrupt register can be found in Section 8.16.
| EVENT | TRIGGER FOR FSM | RESULT (1) | RECOVERY | INTERRUPT BIT | MASK FOR INTERRUPT | LIVE STATUS BIT | INTERRUPT CLEAR |
|---|---|---|---|---|---|---|---|
| BUCK regulator forward current limit triggered | EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A |
EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only |
Depends on PFSM configuration, see PFSM transition diagram | BUCKn_ILIM_INT = 1 | BUCKn_ILIM_MASK | BUCKn_ILIM_STAT | Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active |
| BUCK output or switch short circuit detected | According to BUCKn_GRP_SEL and x_RAIL_TRIG bits | Regulator disable and transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | BUCKn_SC_INT = 1 | N/A | N/A | Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval |
| BUCK output residual voltage violation | BUCKn_RV_SEL = 1
According to BUCKn_GRP_SEL and x_RAIL_TRIG bits BUCKn_RV_SEL = 0 N/A |
BUCKn_RV_SEL = 1
Regulator disable and transition according to FSM trigger and interrupt BUCKn_RV_SEL = 0 N/A |
Depends on PFSM configuration, see PFSM transition diagram | BUCKn_SC_INT = 1 | N/A | N/A | Write 1 to BUCKn_SC_INT bit If BUCKn_SC_INT was set due to a detected residual voltage, this bit can only be read by the MCU if the residual voltage condition is no longer present and the device has performed a succesfull power-up sequence |
| BUCK regulator overvoltage | According to BUCKn_GRP_SEL and x_RAIL_TRIG bits | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | BUCKn_OV_INT = 1 | BUCKn_OV_MASK | BUCKn_OV_STAT | Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present |
| BUCK regulator undervoltage | According to BUCKn_GRP_SEL and x_RAIL_TRIG bits | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | BUCKn_UV_INT = 1 | BUCKn_UV_MASK | BUCKn_UV_STAT | Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present |
| VCCA input overvoltage monitoring | According to VCCA_GRP_SEL and x_RAIL_TRIG bits | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | VCCA_OV_INT = 1 | VCCA_OV_MASK | VCCA_OV_STAT | Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present |
| VCCA input undervoltage monitoring | According to VCCA_GRP_SEL and x_RAIL_TRIG bits | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | VCCA_UV_INT = 1 | VCCA_UV_MASK | VCCA_UV_STAT | Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present |
| VMONx input overvoltage monitoring | According to VMONx_GRP_SEL and X_RAIL_TRIG bits | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | VMONx_OV_INT = 1 | VMONx_OV_MASK | VMONx_OV_STAT | Write 1 to VMONx_OV_INT bit Interrupt is not cleared if the associated fault condition is still present |
| VMONx input undervoltage monitoring | According to VMONx_GRP_SEL and X_RAIL_TRIG bits | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | VMONx_UV_INT = 1 | VMONx_UV_MASK | VMONx_UV_STAT | Write 1 to VMONx_UV_INT bit Interrupt is not cleared if the associated fault condition is still present |
| VMONx residual voltage violation | VMONx_RV_SEL = 1
According to VMONn_GRP_SEL and x_RAIL_TRIG bits VMONx_RV_SEL = 0 N/A |
VMONx_RV_SEL = 1
Transition according to FSM trigger and interrupt VMONx_RV_SEL = 0 N/A |
Depends on PFSM configuration, see PFSM transition diagram | VMONx_RV_INT = 1 | N/A | N/A | Write 1 to VMONx_RV_INT bit |
| Thermal warning | N/A | Interrupt only | Not valid | TWARN_INT = 1 | TWARN_MASK | TWARN_STAT | Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level |
| Thermal shutdown, orderly sequenced | ORDERLY_SHUTDOWN (MODERATE_ERR_INT) | All regulators disabled and Output GPIOx set to low in a sequence and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level | TSD_ORD_INT = 1 | N/A | TSD_ORD_STAT | Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. |
| Thermal shutdown, immediate | IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) | All regulators disabled with pull-down resistors and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level | TSD_IMM_INT = 1 | N/A | TSD_IMM_STAT | Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. |
| BIST error | ORDERLY_SHUTDOWN (MODERATE_ERR_INT) | All regulators disabled and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | BIST_FAIL_INT = 1 | BIST_FAIL_MASK | N/A | Write 1 to BIST_FAIL_INT bit |
| Register CRC error | ORDERLY_SHUTDOWN (MODERATE_ERR_INT) | All regulators disabled and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | REG_CRC_ERR_INT = 1 | REG_CRC_ERR_MASK | N/A | Write 1 to REG_CRC_ERR_INT bit |
| SPMI communication error | ORDERLY_SHUTDOWN (MODERATE_ERR_INT) | All regulators disabled and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | SPMI_ERR_INT = 1 | SPMI_ERR_MASK | N/A | Write 1 to SPMI_ERR_INT bit |
| SPI frame error | N/A | Interrupt only | Not valid | COMM_FRM_ERR_INT = 1 | COMM_FRM_ERR_MASK | N/A | Write 1 to COMM_FRM_ERR_INT bit |
| I2C1 or SPI CRC error | N/A | Interrupt only | Not valid | COMM_CRC_ERR_INT = 1 | COMM_CRC_ERR_MASK | N/A | Write 1 to COMM_CRC_ERR_INT bit |
| I2C1 or SPI address error(4) | N/A | Interrupt only | Not valid | COMM_ADR_ERR_INT = 1 | COMM_ADR_ERR_MASK | N/A | Write 1 to COMM_ADR_ERR_INT bit |
| I2C2 CRC error | N/A | Interrupt only | Not valid | I2C2_CRC_ERR_INT = 1 | I2C2_CRC_ERR_MASK | N/A | Write 1 to I2C2_CRC_ERR_INT bit |
| I2C2 address error(4) | N/A | Interrupt only | Not valid | I2C2_ADR_ERR_INT = 1 | I2C2_ADR_ERR_MASK | N/A | Write 1 to I2C2_ADR_ERR_INT bit |
| PFSM error | IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) | All regulators disabled with pull-down resistors and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. | PFSM_ERR_INT = 1 | N/A | Write 1 to PFSM_ERR_INT bit | |
| EN_DRV pin readback error (monitoring high and low states) | N/A | Interrupt only | Not valid | EN_DRV_READBACK_INT = 1 | EN_DRV_READBACK_MASK | EN_DRV_READBACK_STAT | Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present |
| NINT pin readback error (monitoring low state) | ORDERLY_SHUTDOWN (MODERATE_ERR_INT) | All regulators disabled and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | NINT_READBACK_INT = 1 | NINT_READBACK_MASK | NINT_READBACK_STAT | Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present |
| NRSTOUT pin readback error (monitoring low state) | ORDERLY_SHUTDOWN (MODERATE_ERR_INT) | All regulators disabled and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | NRSTOUT_READBACK_INT = 1 | NRSTOUT_READBACK_MASK | NRSTOUT_READBACK_STAT | Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present |
| NRSTOUT_SOC pin readback error (monitoring low state) | N/A | Interrupt only | Not valid | NRSTOUT_SOC_READBACK_INT = 1 | NRSTOUT_SOC_READBACK_MASK | NRSTOUT_SOC_READBACK_STAT | Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present |
| Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation | N/A | Interrupt only | Not valid | ESM_MCU_PIN_INT = 1 | ESM_MCU_PIN_MASK | N/A | Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present |
| Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) | N/A | Interrupt and EN_DRV = 0 (configurable) | Not valid | ESM_MCU_FAIL_INT = 1 | ESM_MCU_FAIL_MASK | N/A | Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present |
| Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) | ESM_MCU_RST | Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)(1) | Automatically returns to the current operating state after the completion of warm reset | ESM_MCU_RST_INT = 1 | ESM_MCU_RST_MASK | N/A | Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the LP8764-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold |
| External clock is expected, but it is not available or the frequency is not in the valid range | N/A | Interrupt only | Not valid | EXT_CLK_INT = 1(2) | EXT_CLK_MASK | EXT_CLK_STAT | Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present |
| BIST completed successfully | N/A | Interrupt only | Not valid | BIST_PASS_INT = 1 | BIST_PASS_MASK | N/A | Write 1 to BIST_PASS_INT bit |
| Watchdog fail counter above fail threshold | N/A | Interrupt and EN_DRV = 0 | Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH | WD_FAIL_INT = 1 | N/A | N/A | Write 1 to WD_FAIL_INT bit |
| Watchdog fail counter above reset threshold | WD_RST (if WD_RST_EN = 1) | Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)(1) | Automatically returns to the current operating state after the completion of warm reset | WD_RST_INT = 1 | N/A | N/A | Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the LP8764-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold |
| Watchdog long window timeout | WD_RST | Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)(1) | Automatically returns to the current operating state after the completion of warm reset | WD_LONGWIN_TIMEOUT_INT = 1 | N/A | N/A | Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the LP8764-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold |
| Low state in ENABLE pin | TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY | Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting(1) | ENABLE pin rise | N/A | N/A | N/A | N/A |
| ENABLE pin rise | TRIGGER_SU_x | (1) | Not valid | ENABLE_INT = 1 | ENABLE_MASK | ENABLE_STAT | Write 1 to ENABLE_INT bit |
| Fault causing orderly shutdown | ORDERLY_SHUTDOWN | All regulators disabled and Output GPIOx set to low in a sequence and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | ORD_SHUTDOWN_INT | ORD_SHUTDOWN_MASK | N/A | Write 1 to ORD_SHUTDOWN_INT |
| Fault causing immediate shutdown | IMMEDIATE_SHUTDOWN | All regulators disabled (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state | IMM_SHUTDOWN_INT | IMM_SHUTDOWN_MASK | N/A | Write 1 to IMM_SHUTDOWN_INT |
| Power supply error for MCU | MCU_POWER_ERROR | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | MCU_PWR_ERR_INT | MCU_PWR_ERR_MASK | N/A | Write 1 to MCU_PWR_ERR_INT |
| Power supply error for SOC | SOC_POWER_ERROR | Transition according to FSM trigger and interrupt | Depends on PFSM configuration, see PFSM transition diagram | SOC_PWR_ERR_INT | SOC_PWR_ERR_MASK | N/A | Write 1 to SOC_PWR_ERR_INT |
| VCCA over-voltage (VCCAOVP) | IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) | All regulators disabled with pull-down resistors and Output GPIOx set to low immediately and interrupt(1) | Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP | VCCA_OVP_INT = 1 | N/A | VCCA_OVP_STAT | Write 1 to VCCA_OVP _INT bit This bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. |
| GPIO interrupt | According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits | Transition according to FSM trigger and interrupt | Not valid | GPIOx_INT = 1 | GPIOx_RISE_MASK GPIOx_FALL_MASK |
GPIOx_IN | Write 1 to GPIOx_INT bit |
| WKUP1 signals | WKUP1 | Transition to ACTIVE state and interrupt(1) | Not valid | N/A | GPIOx_RISE_MASK GPIOx_FALL_MASK |
GPIOx_IN | Write 1 to GPIOx_INT bit |
| WKUP2 signals | WKUP2 | Transition to MCU ONLY state and interrupt(1) | Not valid | N/A | GPIOx_RISE_MASK GPIOx_FALL_MASK |
GPIOx_IN | Write 1 to GPIOx_INT bit |
| NSLEEP1 signal, NSLEEP1B bit | According to NSLEEP1 and NSLEEP2 | State transition based on NSLEEP1 and NSLEEP2 | Not valid | N/A | NSLEEP1_MASK | GPIOx_IN | N/A |
| NSLEEP2 signal, NSLEEP2B bit | According to NSLEEP1 and NSLEEP2 | State transition based on NSLEEP1 and NSLEEP2 | Not valid | N/A | NSLEEP2_MASK | GPIOx_IN | N/A |
| LDOVINT over- or undervoltage | Reset condition for all logic circuits | All regulators disabled with pull-down resistors and Output GPIOx set to low immediately(1) | Valid LDOVINT voltage | N/A | N/A | N/A | N/A |
| Main clock outside valid frequency | Reset condition for all logic circuits | All regulators disabled with pull-down resistors and Output GPIOx set to low immediately(1) | VCCA power cycle | N/A | N/A | N/A | N/A |
| Recovery counter limit exceeded(3) | ORDERLY_SHUTDOWN | All regulators disabled and Output GPIOx set to low in a sequence(1) | VCCA power cycle | N/A | N/A | N/A | N/A |
| VCCA supply falling below VCCAUVLO | Reset condition for all logic circuits | All regulators disabled with pull-down resistors and Output GPIOx set to low immediately(1) | VCCA voltage rising | N/A | N/A | N/A | N/A |
| First supply detection, VCCA supply rising above VCCAUVLO | TRIGGER_SU_x | Start-up to STARTUP_DEST[1:0] state and interrupt(1) | Not valid | FSD_INT = 1 | FSD_MASK | N/A | Write 1 to FSD_INT bit |