SLLSFT3 November   2025 MC121-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Motor Control
        1. 6.3.1.1 Duty Input
        2. 6.3.1.2 Duty Curve
        3. 6.3.1.3 Motor Start, Speed Change, and Stop
        4. 6.3.1.4 Open-Loop (Duty Cycle) Control
        5. 6.3.1.5 Closed-Loop (Speed) Control
        6. 6.3.1.6 Commutation
          1. 6.3.1.6.1 Hall Sensor
            1. 6.3.1.6.1.1 Field Direction Definition
            2. 6.3.1.6.1.2 Internal Hall Latch Sensor Output
          2. 6.3.1.6.2 Hall Offset
          3. 6.3.1.6.3 Square Commutation
          4. 6.3.1.6.4 Soft Commutation
        7. 6.3.1.7 PWM Modulation Modes
      2. 6.3.2 Protections
        1. 6.3.2.1 Locked Rotor Protection
        2. 6.3.2.2 Current Limit
        3. 6.3.2.3 Overcurrent Protection (OCP)
        4. 6.3.2.4 VM Undervoltage Lockout (UVLO)
        5. 6.3.2.5 VM Over Voltage Protection (OVP)
        6. 6.3.2.6 Thermal Shutdown (TSD)
        7. 6.3.2.7 Integrated Supply (VM) Clamp
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Sleep and Standby Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Test Mode and One-Time Programmable Memory
    5. 6.5 Programming
      1. 6.5.1 I2C Communication
        1. 6.5.1.1 I2C Read
        2. 6.5.1.2 I2C Write
  8. 7 Register Map
    1. 7.1 USR_OTP Registers
    2. 7.2 USR_TM Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Components
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DYM|6
  • DEZ|6
サーマルパッド・メカニカル・データ

5.6 I2C Timing Requirements

MIN NOM MAX UNIT
STANDARD MODE
fSCL SCL Clock frequency 0 100 kHz
tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated
 4 µs
tLOW LOW period of the SCL clock 4.7 µs
tHIGH HIGH period of the SCL clock 4 µs
tSU,STA Setup time for a repeated START condition 4.7 µs
tHD,DAT Data hold time: For I2C bus devices 0.01 3.45 µs
tSU,DAT Data set-up time 250 ns
tR SDA and SCL rise time 1000 ns
tF SDA and SCL fall time 300 ns
tSU,STO Set-up time for STOP condition 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
FAST MODE
fSCL SCL Clock frequency 0 400 kHz
tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs
tLOW LOW period of the SCL clock 1.3 µs
tHIGH HIGH period of the SCL clock 0.6 µs
tSU,STA Setup time for a repeated START condition 0.6 µs
tHD,DAT Data hold time: For I2C bus devices 0.01 0.9 µs
tSU,DAT Data set-up time 50 ns
tR SDA and SCL rise time 300 ns
tF SDA and SCL fall time 300 ns
tSU,STO Set-up time for STOP condition 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
tSP Pulse width of spikes to be supressed by input noise filter  50 ns