Up to 43 I/O ports are implemented.
- P1, P3, P4, and P5 implement 8 bits each. P2 implements 6 bits excluding the I/Os multiplexed
with XIN and XOUT. P6 implements 3 bits.
- All individual I/O bits are independently programmable.
- Any combination of input, output, and interrupt conditions is possible.
- Programmable pullup or pulldown on all ports.
- Edge-selectable interrupt and LPMx.5 wake-up input capability are available for all
GPIOs (up to 43)
- Read and write access to port-control registers is supported by all instructions.
- Ports can be accessed byte-wise or word-wise as a pair.
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, the ports must be configured first and
then the LOCKLPM5 bit must be cleared. For details, see the Configuration After Reset section in the Digital I/O chapter of the MP430FR4xx and MP430FR2xx Family User's Guide.