JAJSMD4D December   2003  – March 2022 OPA1632

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: OPA1632D
    6. 6.6 Electrical Characteristics: OPA1632DGN
    7. 6.7 Typical Characteristics: OPA1632D
    8. 6.8 Typical Characteristics: OPA1632DGN
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Fully-Differential Amplifiers
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Function
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Common-Mode Voltage
        1. 8.1.1.1 Resistor Matching
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PowerPAD Design Considerations
      2. 10.1.2 Power Dissipation and Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Export Control Notice
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics: OPA1632DGN

VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Offset Voltage
Input Offset Voltage±0.5±3mV
vs Power Supply, dcdVOS/dT±5μV°C
vs Power Supply, dcPSRR31613μV/V
Input Bias Current
Input Bias CurrentIB26μA
Input Offset CurrentIOS±100±500nA
Noise
Input Voltage Noisef = 10 kHz1.3nV/√Hz
Input Current Noisef = 10 kHz0.4pA/√Hz
Input Voltage
Common-Mode Input Range(V−) + 1.5(V+) − 1V
Common-Mode Rejection Ratio, dc7490dB
Input Impedance
Input Impedance (each input pin)34 || 4MΩ || pF
Open-Loop Gain
Open-Loop Gain, dc6678dB
Frequency Response
Small-Signal BandwidthG = +1, RF= 348 Ω180MHz
(VO = 100mVPP, Peaking < 0.5 dB)G = +2, RF = 602 Ω90MHz
G = +5, RF = 1.5 kΩ36MHz
G = +10, RF = 3.01 kΩ18MHz
Bandwidth for 0.1dB FlatnessG = +1, VO = 100 mVPP40MHz
Peaking at a Gain of 1VO = 100 mVPP0.5dB
Large-Signal BandwidthG = +2, VO = 20 VPP800kHz
Slew Rate (25% to 75% )G = +150V/μs
Rise and Fall TimeG = +1, VO = 5-V Step100ns
Settling Time to0.1%G = +1, VO = 2-V Step75ns
0.01%G = +1, VO = 2-V Step200ns
Total Harmonic Distortion + NoiseDifferential Input/OutputG = +1, f = 1 kHz,
VO = 3 VRMS
RL = 600 Ω0.0003%
Differential Input/OutputRL = 2 kΩ0.000022%
Single-Ended In/Differential OutRL = 600 Ω0.000059%
Single-Ended In/Differential OutRL = 2 kΩ0.000043%
Intermodulation DistortionDifferential Input/OutputG = +1, SMPTE/DIN, VO = 2 VPPRL = 600 Ω0.00008%
Differential Input/OutputRL = 2 kΩ0.00005%
Single-Ended In/Differential OutRL = 600 Ω0.0001%
Single-Ended In/Differential OutRL = 2 kΩ0.0007%
HeadroomTHD < 0.01%, RL = 2 kΩ20.0VPP
Output
Voltage Output SwingRL = 2 kΩ(V+) − 1.9(V−) + 1.9V
RL = 800 Ω(V+) − 4.5(V−) + 4.5V
Short-Circuit CurrentISCSourcing+5085mA
Sinking−60-85
Closed-Loop Output ImpedanceG = +1, f = 100 kHz0.3Ω
Power-Down(1)
Enable Voltage Threshold(V−) + 2V
Disable Voltage Threshold(V−) + 0.8V
Shutdown Current VENABLE = −15 V 1.7 mA
Shutdown CurrentVS = ±5 V, VENABLE = −5 V0.85mA
Turn-On DelayTime for IQ to Reach 50%2μs
Turn-Off DelayTime for IQ to Reach 50%2μs
Power Supply
Specified Operating Voltage±15V
Operating Voltage±2.5V
Quiescent CurrentIQPer Channel1417.1mA
Temperature Range
Specified Range–40+85°C
Operating Range–40+125°C
Storage Range–65+150°C
Amplifier has internal 50-kΩ pull-up resistor to V+ pin. This enables the amplifier with no connection to shutdown pin.