SBOS079B March   1999  – June 2015 OPA2277 , OPA277 , OPA4277


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for OPA277
    5. 6.5 Thermal Information for OPA2277
    6. 6.6 Thermal Information for OPA4277
    7. 6.7 Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA
    8. 6.8 Electrical Characteristics for OPAx277AIDRM
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Offset Voltage Adjustment
      3. 7.3.3 Input Protection
      4. 7.3.4 Input Bias Current Cancellation
      5. 7.3.5 EMI Rejection Ratio (EMIRR)
        1. EMIRR IN+ Test Configuration
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Second-Order Lowpass Filter
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 8.2.2 Load Cell Amplifier
      3. 8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 DFN Package
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. WEBENCH Filter Designer Tool
        2. TINA-TI (Free Software Download)
        3. TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



  • D|8
  • P|8
  • DRM|8

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to Circuit Board Layout Techniques, SLOA089.
  • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. As shown in Layout Example, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
  • Cleaning the PCB following board assembly is recommended for best performance.
  • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
  • (DFN package only) The leadframe die pad should be soldered to a thermal pad on the PCB. The mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad.
  • (DFN package only) Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long term reliability.

10.2 Layout Example

OPA277 OPA2277 OPA4277 layout_example_sbos079.gifFigure 33. OPA277 Layout Example for the Noninverting Configuration

10.3 DFN Package

The OPAx277 series uses the 8-lead DFN (also known as SON), a QFN package with contacts on only two sides of the package bottom. This leadless, near-chip-scale package maximizes board space and enhances thermal and electrical characteristics through an exposed pad.

DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external leads eliminates bent-lead issues.

The DFN package can be easily mounted using standard printed-circuit-board (PCB) assembly techniques. See QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017), both available for download at

The exposed leadframe die pad on the bottom of the package should be connected to V–.