SBOS079B March   1999  – June 2015 OPA2277 , OPA277 , OPA4277

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for OPA277
    5. 6.5 Thermal Information for OPA2277
    6. 6.6 Thermal Information for OPA4277
    7. 6.7 Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA
    8. 6.8 Electrical Characteristics for OPAx277AIDRM
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Offset Voltage Adjustment
      3. 7.3.3 Input Protection
      4. 7.3.4 Input Bias Current Cancellation
      5. 7.3.5 EMI Rejection Ratio (EMIRR)
        1. 7.3.5.1 EMIRR IN+ Test Configuration
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Second-Order Lowpass Filter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Load Cell Amplifier
      3. 8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 DFN Package
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 WEBENCH Filter Designer Tool
        2. 11.1.1.2 TINA-TI (Free Software Download)
        3. 11.1.1.3 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • P|8
  • DRM|8
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

OPA277 P and D Packages
8-Pin PDIP and SOIC
Top View
OPA277 OPA2277 OPA4277 opa277_po.gif
OPA277 DRM Package
8-Pin VSON
Top View
OPA277 OPA2277 OPA4277 opa277_dfn_po.gif

Pin Functions: OPA277

PIN I/O DESCRIPTION
NO. NAME
1 Offset Trim I Input offset voltage trim (leave floating if not used)
2 –In I Inverting input
3 +In I Noninverting input
4 V– Negative (lowest) power supply
5 NC No internal connection (can be left floating)
6 Output O Output
7 V+ Positive (highest) power supply
8 Offset Trim Input offset voltage trim (leave floating if not used)
OPA2277 P and D Packages
8-Pin PDIP and SOIC
Top View
OPA277 OPA2277 OPA4277 opa2277_po.gif
OPA2277 DRM Package
8-Pin VSON
Top View
OPA277 OPA2277 OPA4277 opa2277_dfn_po.gif

Pin Functions: OPA2277

PIN I/O DESCRIPTION
NAME PDIP, SOIC NO. DFN NO.
Out A 1 1 O Output channel A
–In A 2 2 I Inverting input channel A
+In A 3 3 I Noninverting input channel A
V– 4 4 Negative (lowest) power supply
+In B 5 5 I Noninverting input channel B
–In B 6 6 I Inverting input channel B
Out B 7 8 O Output channel B
V+ 8 7 Positive (highest) power supply
OPA4277 P and D Packages
14 Pins PDIP and SOIC
Top View
OPA277 OPA2277 OPA4277 opa2477_po.gif

Pin Functions: OPA4277

PIN I/O DESCRIPTION
NO. NAME
1 Out A O Output channel A
2 –In A I Inverting input channel A
3 +In A I Noninverting input channel A
4 V+ Positive (highest) power supply
5 +In B I Noninverting input channel B
6 –In B I Inverting input channel B
7 Out B O Output channel B
8 Out C O Output channel C
9 –In C I Inverting input channel C
10 +In C I Noninverting input channel C
11 V– Negative (lowest) power supply
12 +In D I Noninverting input channel D
13 –In D I Inverting input channel D
14 Out D O Output channel D